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[AArch64] The shift right/left and insert immediate builtins expect 3 

source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194407
This commit is contained in:
Chad Rosier 2013-11-11 19:11:19 +00:00
parent d3684a0566
commit 09f5251c4d
2 changed files with 10 additions and 10 deletions
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4
clang/include/clang/Basic/arm_neon.td
View File

@ -859,9 +859,9 @@ def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
// Shift Right And Insert (Immediate)
def SCALAR_SRI_N: SInst<"vsri_n", "ssi", "SlSUl">;
def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
// Shift Left And Insert (Immediate)
def SCALAR_SLI_N: SInst<"vsli_n", "ssi", "SlSUl">;
def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
// Signed/Unsigned Saturating Shift Right Narrow (Immediate)
def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;

16
clang/test/CodeGen/aarch64-neon-intrinsics.c
View File

@ -7616,28 +7616,28 @@ int64_t test_vqshlud_n_s64(int64_t a) {
return (int64_t)vqshlud_n_s64(a, 63);
}
int64_t test_vsrid_n_s64(int64_t a) {
int64_t test_vsrid_n_s64(int64_t a, int64_t b) {
// CHECK-LABEL: test_vsrid_n_s64
// CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
return (int64_t)vsrid_n_s64(a, 63);
return (int64_t)vsrid_n_s64(a, b, 63);
}
uint64_t test_vsrid_n_u64(uint64_t a) {
uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) {
// CHECK-LABEL: test_vsrid_n_u64
// CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
return (uint64_t)vsrid_n_u64(a, 63);
return (uint64_t)vsrid_n_u64(a, b, 63);
}
int64_t test_vslid_n_s64(int64_t a) {
int64_t test_vslid_n_s64(int64_t a, int64_t b) {
// CHECK-LABEL: test_vslid_n_s64
// CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
return (int64_t)vslid_n_s64(a, 63);
return (int64_t)vslid_n_s64(a, b, 63);
}
uint64_t test_vslid_n_u64(uint64_t a) {
uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
// CHECK-LABEL: test_vslid_n_u64
// CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
return (uint64_t)vslid_n_u64(a, 63);
return (uint64_t)vslid_n_u64(a, b, 63);
}
int8_t test_vqshrnh_n_s16(int16_t a) {