forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select VALU G_AMDGPU_FFBH_U32
llvm-svn: 373944
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@ -235,7 +235,7 @@ defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>;
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defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>;
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defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>;
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defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>;
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defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32, AMDGPUffbh_u32>;
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defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>;
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defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32, AMDGPUffbh_i32>;
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@ -1,5 +1,5 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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@ -36,9 +36,9 @@ body: |
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; CHECK-LABEL: name: ffbh_u32_s32_v_v
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
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; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
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S_ENDPGM 0, implicit %1
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@ -58,9 +58,9 @@ body: |
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; CHECK-LABEL: name: ffbh_u32_v_s
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
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; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
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; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
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S_ENDPGM 0, implicit %1
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