forked from OSchip/llvm-project
Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range. Since there is not direct object emitter at this time, it does not have any material affect because the assembler sorts this out. But we need to know for the actual constant island work. We track the difference by putting # 16 inst in the comments. llvm-svn: 194766
This commit is contained in:
Reed Kotler
parent
00e65b2afe
commit
09e59155ef
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@ -174,57 +174,57 @@ Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case Mips::SelBneZ:
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return emitSel16(Mips::BnezRxImm16, MI, BB);
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case Mips::SelTBteqZCmpi:
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return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
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return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
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case Mips::SelTBteqZSlti:
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return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
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return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SelTBteqZSltiu:
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return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
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return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SelTBtneZCmpi:
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return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
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return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
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case Mips::SelTBtneZSlti:
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return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
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return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SelTBtneZSltiu:
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return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
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return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SelTBteqZCmp:
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return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
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return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBteqZSlt:
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return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
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return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBteqZSltu:
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return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
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return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
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case Mips::SelTBtneZCmp:
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return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
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return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBtneZSlt:
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return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
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return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBtneZSltu:
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return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
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return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
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case Mips::BteqzT8CmpX16:
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return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
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case Mips::BteqzT8SltX16:
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return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
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case Mips::BteqzT8SltuX16:
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// TBD: figure out a way to get this or remove the instruction
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// altogether.
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return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
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case Mips::BtnezT8CmpX16:
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return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
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case Mips::BtnezT8SltX16:
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return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
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case Mips::BtnezT8SltuX16:
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// TBD: figure out a way to get this or remove the instruction
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// altogether.
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return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
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return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
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case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
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Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
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Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
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Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
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Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
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case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
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Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
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case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
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Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
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break;
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case Mips::SltCCRxRy16:
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return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
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@ -152,13 +152,17 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
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case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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case Mips::Btnez16: return Mips::Bteqz16;
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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case Mips::Bteqz16: return Mips::Btnez16;
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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@ -441,6 +445,8 @@ Mips16InstrInfo::basicLoadImmediate(
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unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
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return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
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Opc == Mips::Bimm16 ||
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Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
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Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
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Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
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Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
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Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
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@ -51,7 +51,10 @@ class FI816_ins_base<bits<3> _func, string asmstr,
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FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
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[], itin>;
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class FI816_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
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class FI816_SP_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
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@ -627,6 +630,10 @@ def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
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// Purpose: Branch on T Equal to Zero (Extended)
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// To test special register T then do a PC-relative conditional branch.
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//
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def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
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let Uses = [T8];
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}
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def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
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let Uses = [T8];
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}
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@ -650,6 +657,11 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
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// Purpose: Branch on T Not Equal to Zero (Extended)
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// To test special register T then do a PC-relative conditional branch.
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//
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def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 {
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let Uses = [T8];
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}
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def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
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let Uses = [T8];
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}
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@ -1427,7 +1439,7 @@ def: Mips16Pat
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def: Mips16Pat
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<(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
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(BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
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(BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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@ -1489,7 +1501,7 @@ def: Mips16Pat
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def: Mips16Pat
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<(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
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(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
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(BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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@ -1497,7 +1509,7 @@ def: Mips16Pat
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//
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def: Mips16Pat
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<(brcond CPU16Regs:$rx, bb:$targ16),
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(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
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(BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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@ -0,0 +1,20 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short
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@i = global i32 0, align 4
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@j = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define i32 @main() #0 {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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%. = select i1 %cmp, i32 10, i32 55
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store i32 %., i32* @j, align 4
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; cond-b-short: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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ret i32 0
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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@ -0,0 +1,24 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short
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@i = global i32 0, align 4
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@j = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define i32 @main() #0 {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.end
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; cond-b-short: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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if.then: ; preds = %entry
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store i32 10, i32* @j, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 0
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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@ -0,0 +1,21 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short
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@i = global i32 1, align 4
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@j = global i32 2, align 4
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@k = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define void @t() #0 {
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entry:
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%0 = load i32* @i, align 4
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%1 = load i32* @j, align 4
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%cmp = icmp eq i32 %0, %1
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%cond = select i1 %cmp, i32 1, i32 2
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store i32 %cond, i32* @k, align 4
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ret void
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; cond-b-short: bteqz $BB0_{{[0-9]+}} # 16 bit inst
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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@ -0,0 +1,21 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short
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@i = global i32 1, align 4
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@j = global i32 2, align 4
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@k = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define void @t() #0 {
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entry:
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%0 = load i32* @i, align 4
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%1 = load i32* @j, align 4
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%cmp = icmp ne i32 %0, %1
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%cond = select i1 %cmp, i32 1, i32 2
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store i32 %cond, i32* @k, align 4
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; cond-b-short: btnez $BB0_{{[0-9]+}} # 16 bit inst
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ret void
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}
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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