forked from OSchip/llvm-project
Allow targets to select source order pre-RA scheduler.
llvm-svn: 148033
This commit is contained in:
parent
4a6e778aae
commit
09cc429cb1
|
@ -56,6 +56,7 @@ namespace llvm {
|
|||
namespace Sched {
|
||||
enum Preference {
|
||||
None, // No preference
|
||||
Source, // Follow source order.
|
||||
RegPressure, // Scheduling for lowest register pressure.
|
||||
Hybrid, // Scheduling for both latency and register pressure.
|
||||
ILP // Scheduling for ILP in low register pressure mode.
|
||||
|
|
|
@ -218,7 +218,8 @@ namespace llvm {
|
|||
CodeGenOpt::Level OptLevel) {
|
||||
const TargetLowering &TLI = IS->getTargetLowering();
|
||||
|
||||
if (OptLevel == CodeGenOpt::None)
|
||||
if (OptLevel == CodeGenOpt::None ||
|
||||
TLI.getSchedulingPreference() == Sched::Source)
|
||||
return createSourceListDAGScheduler(IS, OptLevel);
|
||||
if (TLI.getSchedulingPreference() == Sched::RegPressure)
|
||||
return createBURRListDAGScheduler(IS, OptLevel);
|
||||
|
|
Loading…
Reference in New Issue