forked from OSchip/llvm-project
Revert "[RISCV] implement li pseudo instruction"
Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
This commit is contained in:
Alex Bradbury
parent
5832eb4cfd
commit
099c720426
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@ -9,7 +9,6 @@
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVMCPseudoExpansion.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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@ -23,11 +22,8 @@
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <limits>
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using namespace llvm;
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// Include the auto-generated portion of the compress emitter.
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@ -45,7 +41,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
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unsigned Kind) override;
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bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
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int64_t Lower, int64_t Upper, Twine Msg);
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int Lower, int Upper, Twine Msg);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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@ -59,12 +55,6 @@ class RISCVAsmParser : public MCTargetAsmParser {
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bool ParseDirective(AsmToken DirectiveID) override;
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/// Helper for emitting MC instructions that have been successfully matched
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/// by MatchAndEmitInstruction. Modifications to the emitted instructions,
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/// like the expansion of pseudo instructions (e.g., "li"), can be performed
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/// in this method.
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bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
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// Auto-generated instruction matching functions
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#define GET_ASSEMBLER_HEADER
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#include "RISCVGenAsmMatcher.inc"
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@ -220,18 +210,6 @@ public:
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return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid;
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}
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bool isImmXLen() const {
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int64_t Imm;
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RISCVMCExpr::VariantKind VK;
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if (!isImm())
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return false;
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bool IsConstantImm = evaluateConstantImm(Imm, VK);
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// Given only Imm, ensuring that the actually specified constant is either
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// a signed or unsigned 64-bit number is unfortunately impossible.
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bool IsInRange = isRV64() ? true : isInt<32>(Imm) || isUInt<32>(Imm);
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return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
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}
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bool isUImmLog2XLen() const {
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int64_t Imm;
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RISCVMCExpr::VariantKind VK;
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@ -605,7 +583,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
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}
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bool RISCVAsmParser::generateImmOutOfRangeError(
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OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
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OperandVector &Operands, uint64_t ErrorInfo, int Lower, int Upper,
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Twine Msg = "immediate must be an integer in the range") {
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SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
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@ -621,8 +599,14 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
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default:
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break;
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case Match_Success:
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return processInstruction(Inst, IDLoc, Out);
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case Match_Success: {
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MCInst CInst;
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bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
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CInst.setLoc(IDLoc);
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Inst.setLoc(IDLoc);
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Out.EmitInstruction((Res ? CInst : Inst), getSTI());
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return false;
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}
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case Match_MissingFeature:
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return Error(IDLoc, "instruction use requires an option to be enabled");
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case Match_MnemonicFail:
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@ -639,14 +623,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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}
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return Error(ErrorLoc, "invalid operand for instruction");
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}
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case Match_InvalidImmXLen:
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if (isRV64()) {
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SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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return Error(ErrorLoc, "operand must be a constant 64-bit integer");
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}
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return generateImmOutOfRangeError(Operands, ErrorInfo,
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std::numeric_limits<int32_t>::min(),
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std::numeric_limits<uint32_t>::max());
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case Match_InvalidUImmLog2XLen:
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if (isRV64())
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
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@ -991,31 +967,6 @@ bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr,
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return Kind != RISCVMCExpr::VK_RISCV_Invalid;
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}
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bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out) {
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Inst.setLoc(IDLoc);
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switch (Inst.getOpcode()) {
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case RISCV::PseudoLI: {
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auto Reg = Inst.getOperand(0).getReg();
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int64_t Imm = Inst.getOperand(1).getImm();
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// On RV32 the immediate here can either be a signed or an unsigned
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// 32-bit number. Sign extension has to be performed to ensure that Imm
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// represents the expected signed 64-bit number.
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if (!isRV64())
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Imm = SignExtend64<32>(Imm);
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emitRISCVLoadImm(Reg, Imm, Out, STI);
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return false;
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}
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}
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MCInst CInst;
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bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
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CInst.setLoc(IDLoc);
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Out.EmitInstruction((Res ? CInst : Inst), getSTI());
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return false;
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}
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bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
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extern "C" void LLVMInitializeRISCVAsmParser() {
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@ -4,7 +4,6 @@ add_llvm_library(LLVMRISCVDesc
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RISCVMCAsmInfo.cpp
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RISCVMCCodeEmitter.cpp
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RISCVMCExpr.cpp
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RISCVMCPseudoExpansion.cpp
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RISCVMCTargetDesc.cpp
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RISCVTargetStreamer.cpp
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RISCVELFStreamer.cpp
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@ -1,101 +0,0 @@
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//===-- RISCVMCPseudoExpansion.cpp - RISCV MC Pseudo Expansion ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file provides helpers to expand pseudo MC instructions that are usable
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/// in the AsmParser and the AsmPrinter.
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///
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//===----------------------------------------------------------------------===//
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#include "RISCVMCPseudoExpansion.h"
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#include "RISCVMCTargetDesc.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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using namespace llvm;
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void llvm::emitRISCVLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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if (isInt<32>(Value)) {
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// Emits the MC instructions for loading a 32-bit constant into a register.
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//
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// Depending on the active bits in the immediate Value v, the following
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// instruction sequences are emitted:
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//
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// v == 0 : ADDI(W)
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// v[0,12) != 0 && v[12,32) == 0 : ADDI(W)
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// v[0,12) == 0 && v[12,32) != 0 : LUI
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// v[0,32) != 0 : LUI+ADDI(W)
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//
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int64_t Hi20 = ((Value + 0x800) >> 12) & 0xFFFFF;
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int64_t Lo12 = SignExtend64<12>(Value);
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unsigned SrcReg = RISCV::X0;
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if (Hi20) {
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Out.EmitInstruction(
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MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Hi20), *STI);
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SrcReg = DestReg;
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}
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if (Lo12 || Hi20 == 0) {
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unsigned AddiOpcode =
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STI->hasFeature(RISCV::Feature64Bit) ? RISCV::ADDIW : RISCV::ADDI;
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Out.EmitInstruction(
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MCInstBuilder(AddiOpcode).addReg(DestReg).addReg(SrcReg).addImm(Lo12),
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*STI);
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}
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return;
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}
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assert(STI->hasFeature(RISCV::Feature64Bit) &&
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"Target must be 64-bit to support a >32-bit constant");
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// In the worst case, for a full 64-bit constant, a sequence of 8 instructions
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// (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
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// that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
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// while the following ADDI instructions contribute up to 12 bits each.
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//
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// On the first glance, implementing this seems to be possible by simply
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// emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
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// shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
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// fact that ADDI performs a sign extended addition, doing it like that would
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// only be possible when at most 11 bits of the ADDI instructions are used.
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// Using all 12 bits of the ADDI instructions, like done by GAS, actually
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// requires that the constant is processed starting with the least significant
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// bit.
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//
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// In the following, constants are processed from LSB to MSB but instruction
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// emission is performed from MSB to LSB by recursively calling
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// emitRISCVLoadImm. In each recursion, first the lowest 12 bits are removed
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// from the constant and the optimal shift amount, which can be greater than
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// 12 bits if the constant is sparse, is determined. Then, the shifted
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// remaining constant is processed recursively and gets emitted as soon as it
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// fits into 32 bits. The emission of the shifts and additions is subsequently
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// performed when the recursion returns.
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//
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int64_t Lo12 = SignExtend64<12>(Value);
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int64_t Hi52 = (Value + 0x800) >> 12;
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int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
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Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
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emitRISCVLoadImm(DestReg, Hi52, Out, STI);
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Out.EmitInstruction(MCInstBuilder(RISCV::SLLI)
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.addReg(DestReg)
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.addReg(DestReg)
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.addImm(ShiftAmount),
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*STI);
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if (Lo12)
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Out.EmitInstruction(
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MCInstBuilder(RISCV::ADDI).addReg(DestReg).addReg(DestReg).addImm(Lo12),
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*STI);
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}
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@ -1,29 +0,0 @@
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//===-- RISCVMCPseudoExpansion.h - RISCV MC Pseudo Expansion ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// This file describes helpers to expand pseudo MC instructions that are usable
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/// in the AsmParser and the AsmPrinter.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H
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#include <cstdint>
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namespace llvm {
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class MCStreamer;
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class MCSubtargetInfo;
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void emitRISCVLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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} // namespace llvm
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#endif
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@ -15,7 +15,6 @@
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#include "RISCV.h"
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#include "InstPrinter/RISCVInstPrinter.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVMCPseudoExpansion.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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@ -79,14 +78,6 @@ void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (emitPseudoExpansionLowering(*OutStreamer, MI))
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return;
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if (MI->getOpcode() == RISCV::PseudoLI) {
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const MachineOperand &DstRegOp = MI->getOperand(0);
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const MachineOperand &ImmOp = MI->getOperand(1);
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emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), *OutStreamer,
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&getSubtargetInfo());
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return;
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}
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MCInst TmpInst;
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LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
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EmitToStreamer(*OutStreamer, TmpInst);
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@ -179,39 +179,15 @@ void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() {
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SDValue Base = N->getOperand(BaseOpIdx);
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// If the base is an ADDI or PseudoLI, we can either merge it or at least
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// sink the lowest 12 bits into the load/store.
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if (!Base.isMachineOpcode() || (Base.getMachineOpcode() != RISCV::ADDI &&
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Base.getMachineOpcode() != RISCV::PseudoLI))
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// If the base is an ADDI, we can merge it in to the load/store.
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if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
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continue;
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SDValue ImmOperand;
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SDValue Parent;
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if (Base.getMachineOpcode() == RISCV::PseudoLI) {
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ImmOperand = Base.getOperand(0);
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auto Const = dyn_cast<ConstantSDNode>(ImmOperand);
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if (!Const || (Const->getSExtValue() & 0xFFF) == 0)
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continue;
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int64_t Hi52 = (Const->getSExtValue() + 0x800) & ~0xFFF;
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SDValue HiVal = CurDAG->getTargetConstant(Hi52, SDLoc(ImmOperand),
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ImmOperand.getValueType());
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Parent =
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SDValue(CurDAG->getMachineNode(RISCV::PseudoLI, SDLoc(ImmOperand),
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ImmOperand.getValueType(), HiVal),
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0);
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int64_t Lo12 = SignExtend64<12>(Const->getSExtValue());
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ImmOperand = CurDAG->getTargetConstant(Lo12, SDLoc(ImmOperand),
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ImmOperand.getValueType());
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} else {
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Parent = Base.getOperand(0);
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ImmOperand = Base.getOperand(1);
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SDValue ImmOperand = Base.getOperand(1);
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if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
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ImmOperand =
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CurDAG->getTargetConstant(Const->getSExtValue(), SDLoc(ImmOperand),
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ImmOperand.getValueType());
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ImmOperand = CurDAG->getTargetConstant(
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Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());
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} else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
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ImmOperand = CurDAG->getTargetGlobalAddress(
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GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
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@ -219,22 +195,25 @@ void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() {
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} else {
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continue;
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}
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}
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DEBUG(dbgs() << "Folding add-immediate or PseudoLI into mem-op:\nBase: ");
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DEBUG(Base.dump(CurDAG));
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DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
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DEBUG(Base->dump(CurDAG));
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DEBUG(dbgs() << "\nN: ");
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DEBUG(N->dump(CurDAG));
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DEBUG(dbgs() << "\n");
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// Modify the offset operand of the load/store.
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if (BaseOpIdx == 0) // Load
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CurDAG->UpdateNodeOperands(N, Parent, ImmOperand, N->getOperand(2));
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CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand,
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N->getOperand(2));
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else // Store
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CurDAG->UpdateNodeOperands(N, N->getOperand(0), Parent, ImmOperand,
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N->getOperand(3));
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CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0),
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ImmOperand, N->getOperand(3));
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// The add-immediate may now be dead, in which case remove it.
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if (Base.getNode()->use_empty())
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CurDAG->RemoveDeadNode(Base.getNode());
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}
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CurDAG->RemoveDeadNodes();
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}
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// Remove redundant BuildPairF64+SplitF64 pairs. i.e. cases where an f64 is
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@ -102,8 +102,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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}
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// Pseudo instructions
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class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
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: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
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class Pseudo<dag outs, dag ins, list<dag> pattern>
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: RVInst<outs, ins, "", "", pattern, InstFormatPseudo> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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@ -112,8 +112,17 @@ void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
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MachineInstr::MIFlag Flag) const {
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assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
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BuildMI(MBB, MBBI, DL, get(RISCV::PseudoLI), DstReg)
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.addImm(Val)
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// TODO: If the value can be materialized using only one instruction, only
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// insert a single instruction.
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uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
|
||||
uint64_t Lo12 = SignExtend64<12>(Val);
|
||||
BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
|
||||
.addImm(Hi20)
|
||||
.setMIFlag(Flag);
|
||||
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
|
||||
.addReg(DstReg, RegState::Kill)
|
||||
.addImm(Lo12)
|
||||
.setMIFlag(Flag);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -43,12 +43,6 @@ def SelectCC : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
|
|||
// Operand and SDNode transformation definitions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class ImmXLenAsmOperand<string prefix, string suffix = ""> : AsmOperandClass {
|
||||
let Name = prefix # "ImmXLen" # suffix;
|
||||
let RenderMethod = "addImmOperands";
|
||||
let DiagnosticType = !strconcat("Invalid", Name);
|
||||
}
|
||||
|
||||
class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
|
||||
let Name = prefix # "Imm" # width # suffix;
|
||||
let RenderMethod = "addImmOperands";
|
||||
|
|
@ -160,9 +154,7 @@ def simm21_lsb0 : Operand<OtherVT> {
|
|||
}
|
||||
|
||||
// A parameterized register class alternative to i32imm/i64imm from Target.td.
|
||||
def ixlenimm : Operand<XLenVT> {
|
||||
let ParserMatchClass = ImmXLenAsmOperand<"">;
|
||||
}
|
||||
def ixlenimm : Operand<XLenVT>;
|
||||
|
||||
// Standalone (codegen-only) immleaf patterns.
|
||||
def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
|
||||
|
|
@ -426,16 +418,7 @@ def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
|
|||
// TODO RV64I: sd
|
||||
|
||||
def : InstAlias<"nop", (ADDI X0, X0, 0)>;
|
||||
|
||||
// Note that a size of 8 is currently correct because only 32-bit immediates
|
||||
// are emitted as PseudoLI during codegen. Emitting larger constants as
|
||||
// PseudoLI is probably not the best idea anyway given that up to
|
||||
// 8 32-bit instructions are needed to generate an arbitrary 64-bit immediate.
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
|
||||
isCodeGenOnly = 0, isAsmParserOnly = 1 in
|
||||
def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm:$imm), [],
|
||||
"li", "$rd, $imm">;
|
||||
|
||||
// TODO li
|
||||
def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
|
||||
def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
|
||||
def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
|
||||
|
|
@ -538,7 +521,8 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
|
|||
/// Immediates
|
||||
|
||||
def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
|
||||
def : Pat<(simm32:$imm), (PseudoLI imm:$imm)>;
|
||||
// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits.
|
||||
def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
|
||||
|
||||
/// Simple arithmetic operations
|
||||
|
||||
|
|
|
|||
|
|
@ -15,9 +15,10 @@ declare i32 @llvm.ctpop.i32(i32)
|
|||
define i16 @test_bswap_i16(i16 %a) nounwind {
|
||||
; RV32I-LABEL: test_bswap_i16:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: slli a1, a0, 8
|
||||
; RV32I-NEXT: lui a2, 4080
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 4080
|
||||
; RV32I-NEXT: mv a1, a1
|
||||
; RV32I-NEXT: slli a2, a0, 8
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: slli a0, a0, 24
|
||||
; RV32I-NEXT: or a0, a0, a1
|
||||
; RV32I-NEXT: srli a0, a0, 16
|
||||
|
|
@ -29,15 +30,16 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
|
|||
define i32 @test_bswap_i32(i32 %a) nounwind {
|
||||
; RV32I-LABEL: test_bswap_i32:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: srli a1, a0, 8
|
||||
; RV32I-NEXT: lui a2, 16
|
||||
; RV32I-NEXT: addi a2, a2, -256
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 16
|
||||
; RV32I-NEXT: addi a1, a1, -256
|
||||
; RV32I-NEXT: srli a2, a0, 8
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: srli a2, a0, 24
|
||||
; RV32I-NEXT: or a1, a1, a2
|
||||
; RV32I-NEXT: slli a2, a0, 8
|
||||
; RV32I-NEXT: lui a3, 4080
|
||||
; RV32I-NEXT: and a2, a2, a3
|
||||
; RV32I-NEXT: lui a2, 4080
|
||||
; RV32I-NEXT: mv a2, a2
|
||||
; RV32I-NEXT: slli a3, a0, 8
|
||||
; RV32I-NEXT: and a2, a3, a2
|
||||
; RV32I-NEXT: slli a0, a0, 24
|
||||
; RV32I-NEXT: or a0, a0, a2
|
||||
; RV32I-NEXT: or a0, a0, a1
|
||||
|
|
@ -49,24 +51,25 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
|
|||
define i64 @test_bswap_i64(i64 %a) nounwind {
|
||||
; RV32I-LABEL: test_bswap_i64:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: lui a2, 16
|
||||
; RV32I-NEXT: addi a3, a2, -256
|
||||
; RV32I-NEXT: srli a2, a1, 8
|
||||
; RV32I-NEXT: lui a3, 16
|
||||
; RV32I-NEXT: addi a3, a3, -256
|
||||
; RV32I-NEXT: and a2, a2, a3
|
||||
; RV32I-NEXT: srli a4, a1, 24
|
||||
; RV32I-NEXT: or a2, a2, a4
|
||||
; RV32I-NEXT: slli a4, a1, 8
|
||||
; RV32I-NEXT: lui a5, 4080
|
||||
; RV32I-NEXT: and a4, a4, a5
|
||||
; RV32I-NEXT: lui a4, 4080
|
||||
; RV32I-NEXT: mv a4, a4
|
||||
; RV32I-NEXT: slli a5, a1, 8
|
||||
; RV32I-NEXT: and a5, a5, a4
|
||||
; RV32I-NEXT: slli a1, a1, 24
|
||||
; RV32I-NEXT: or a1, a1, a4
|
||||
; RV32I-NEXT: or a1, a1, a5
|
||||
; RV32I-NEXT: or a2, a1, a2
|
||||
; RV32I-NEXT: srli a1, a0, 8
|
||||
; RV32I-NEXT: and a1, a1, a3
|
||||
; RV32I-NEXT: srli a3, a0, 24
|
||||
; RV32I-NEXT: or a1, a1, a3
|
||||
; RV32I-NEXT: slli a3, a0, 8
|
||||
; RV32I-NEXT: and a3, a3, a5
|
||||
; RV32I-NEXT: and a3, a3, a4
|
||||
; RV32I-NEXT: slli a0, a0, 24
|
||||
; RV32I-NEXT: or a0, a0, a3
|
||||
; RV32I-NEXT: or a1, a0, a1
|
||||
|
|
@ -87,10 +90,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -103,10 +106,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: j .LBB3_3
|
||||
|
|
@ -133,10 +136,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -149,10 +152,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: j .LBB4_3
|
||||
|
|
@ -176,10 +179,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -192,10 +195,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: j .LBB5_3
|
||||
|
|
@ -226,9 +229,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
|
|||
; RV32I-NEXT: or a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 16
|
||||
; RV32I-NEXT: or a0, a0, a1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
|
|
@ -243,10 +246,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: j .LBB6_3
|
||||
|
|
@ -278,26 +281,26 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
|
|||
; RV32I-NEXT: addi a0, a0, -1
|
||||
; RV32I-NEXT: not a1, s3
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi s5, a1, 1365
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui s5, 349525
|
||||
; RV32I-NEXT: addi s5, s5, 1365
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui s6, 209715
|
||||
; RV32I-NEXT: addi s6, s6, 819
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi s6, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi s4, a1, 257
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui s8, 61681
|
||||
; RV32I-NEXT: addi s8, s8, -241
|
||||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi s8, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: lui s4, 4112
|
||||
; RV32I-NEXT: addi s4, s4, 257
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
|
|
@ -348,10 +351,10 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -364,10 +367,10 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
|
|
@ -385,10 +388,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -401,10 +404,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
|
|
@ -422,10 +425,10 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
|
|||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -438,10 +441,10 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
|
|
@ -469,26 +472,26 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
|
|||
; RV32I-NEXT: addi a0, a0, -1
|
||||
; RV32I-NEXT: not a1, s3
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi s5, a1, 1365
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui s5, 349525
|
||||
; RV32I-NEXT: addi s5, s5, 1365
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui s6, 209715
|
||||
; RV32I-NEXT: addi s6, s6, 819
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi s6, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi s4, a1, 257
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui s8, 61681
|
||||
; RV32I-NEXT: addi s8, s8, -241
|
||||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi s8, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: lui s4, 4112
|
||||
; RV32I-NEXT: addi s4, s4, 257
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
|
|
@ -536,10 +539,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
|
|||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp)
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: lui a2, 349525
|
||||
; RV32I-NEXT: addi a2, a2, 1365
|
||||
; RV32I-NEXT: and a1, a1, a2
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi a1, a1, 819
|
||||
|
|
@ -552,10 +555,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
|
|||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi a1, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi a1, a1, 257
|
||||
; RV32I-NEXT: lui a2, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
|
|
|
|||
|
|
@ -85,13 +85,14 @@ define i32 @caller_scalars() nounwind {
|
|||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: addi sp, sp, -16
|
||||
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 262464
|
||||
; RV32I-FPELIM-NEXT: mv a6, a0
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars)
|
||||
; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 1
|
||||
; RV32I-FPELIM-NEXT: addi a1, zero, 2
|
||||
; RV32I-FPELIM-NEXT: addi a3, zero, 3
|
||||
; RV32I-FPELIM-NEXT: addi a4, zero, 4
|
||||
; RV32I-FPELIM-NEXT: lui a6, 262464
|
||||
; RV32I-FPELIM-NEXT: mv a2, zero
|
||||
; RV32I-FPELIM-NEXT: mv a5, zero
|
||||
; RV32I-FPELIM-NEXT: jalr a7
|
||||
|
|
@ -105,13 +106,14 @@ define i32 @caller_scalars() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
|
||||
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||||
; RV32I-WITHFP-NEXT: lui a0, 262464
|
||||
; RV32I-WITHFP-NEXT: mv a6, a0
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars)
|
||||
; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 1
|
||||
; RV32I-WITHFP-NEXT: addi a1, zero, 2
|
||||
; RV32I-WITHFP-NEXT: addi a3, zero, 3
|
||||
; RV32I-WITHFP-NEXT: addi a4, zero, 4
|
||||
; RV32I-WITHFP-NEXT: lui a6, 262464
|
||||
; RV32I-WITHFP-NEXT: mv a2, zero
|
||||
; RV32I-WITHFP-NEXT: mv a5, zero
|
||||
; RV32I-WITHFP-NEXT: jalr a7
|
||||
|
|
@ -185,8 +187,6 @@ define i32 @caller_large_scalars() nounwind {
|
|||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: addi sp, sp, -48
|
||||
; RV32I-FPELIM-NEXT: sw ra, 44(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 524272
|
||||
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 4(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
|
||||
|
|
@ -195,6 +195,9 @@ define i32 @caller_large_scalars() nounwind {
|
|||
; RV32I-FPELIM-NEXT: sw zero, 28(sp)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 1
|
||||
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 524272
|
||||
; RV32I-FPELIM-NEXT: mv a0, a0
|
||||
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars)
|
||||
; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars)
|
||||
; RV32I-FPELIM-NEXT: addi a0, sp, 24
|
||||
|
|
@ -210,8 +213,6 @@ define i32 @caller_large_scalars() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw ra, 44(sp)
|
||||
; RV32I-WITHFP-NEXT: sw s0, 40(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 48
|
||||
; RV32I-WITHFP-NEXT: lui a0, 524272
|
||||
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
|
||||
|
|
@ -220,6 +221,9 @@ define i32 @caller_large_scalars() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 1
|
||||
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, 524272
|
||||
; RV32I-WITHFP-NEXT: mv a0, a0
|
||||
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars)
|
||||
; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars)
|
||||
; RV32I-WITHFP-NEXT: addi a0, s0, -24
|
||||
|
|
@ -302,8 +306,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
|
|||
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 9
|
||||
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 524272
|
||||
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
|
||||
|
|
@ -312,6 +314,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
|
|||
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 8
|
||||
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 524272
|
||||
; RV32I-FPELIM-NEXT: mv a0, a0
|
||||
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
|
||||
; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 1
|
||||
|
|
@ -337,8 +342,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 9
|
||||
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
|
||||
; RV32I-WITHFP-NEXT: lui a0, 524272
|
||||
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
|
||||
|
|
@ -347,6 +350,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 8
|
||||
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, 524272
|
||||
; RV32I-WITHFP-NEXT: mv a0, a0
|
||||
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
|
||||
; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 1
|
||||
|
|
@ -770,6 +776,8 @@ define void @caller_aligned_stack() nounwind {
|
|||
; RV32I-FPELIM-NEXT: lui a0, 335544
|
||||
; RV32I-FPELIM-NEXT: addi a0, a0, 1311
|
||||
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 688509
|
||||
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(callee_aligned_stack)
|
||||
; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_aligned_stack)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 1
|
||||
|
|
@ -777,8 +785,6 @@ define void @caller_aligned_stack() nounwind {
|
|||
; RV32I-FPELIM-NEXT: addi a2, sp, 32
|
||||
; RV32I-FPELIM-NEXT: addi a3, zero, 12
|
||||
; RV32I-FPELIM-NEXT: addi a4, zero, 13
|
||||
; RV32I-FPELIM-NEXT: lui a5, 688509
|
||||
; RV32I-FPELIM-NEXT: addi a5, a5, -2048
|
||||
; RV32I-FPELIM-NEXT: addi a6, zero, 4
|
||||
; RV32I-FPELIM-NEXT: addi a7, zero, 14
|
||||
; RV32I-FPELIM-NEXT: jalr t0
|
||||
|
|
@ -818,6 +824,8 @@ define void @caller_aligned_stack() nounwind {
|
|||
; RV32I-WITHFP-NEXT: lui a0, 335544
|
||||
; RV32I-WITHFP-NEXT: addi a0, a0, 1311
|
||||
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, 688509
|
||||
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(callee_aligned_stack)
|
||||
; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_aligned_stack)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 1
|
||||
|
|
@ -825,8 +833,6 @@ define void @caller_aligned_stack() nounwind {
|
|||
; RV32I-WITHFP-NEXT: addi a2, s0, -32
|
||||
; RV32I-WITHFP-NEXT: addi a3, zero, 12
|
||||
; RV32I-WITHFP-NEXT: addi a4, zero, 13
|
||||
; RV32I-WITHFP-NEXT: lui a5, 688509
|
||||
; RV32I-WITHFP-NEXT: addi a5, a5, -2048
|
||||
; RV32I-WITHFP-NEXT: addi a6, zero, 4
|
||||
; RV32I-WITHFP-NEXT: addi a7, zero, 14
|
||||
; RV32I-WITHFP-NEXT: jalr t0
|
||||
|
|
@ -981,6 +987,7 @@ define fp128 @callee_large_scalar_ret() nounwind {
|
|||
; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
|
||||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: lui a1, 524272
|
||||
; RV32I-FPELIM-NEXT: mv a1, a1
|
||||
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 8(a0)
|
||||
; RV32I-FPELIM-NEXT: sw zero, 4(a0)
|
||||
|
|
@ -994,6 +1001,7 @@ define fp128 @callee_large_scalar_ret() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||||
; RV32I-WITHFP-NEXT: lui a1, 524272
|
||||
; RV32I-WITHFP-NEXT: mv a1, a1
|
||||
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, 8(a0)
|
||||
; RV32I-WITHFP-NEXT: sw zero, 4(a0)
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ define float @fneg_s(float %a) nounwind {
|
|||
; RV32IF-LABEL: fneg_s:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: lui a1, 524288
|
||||
; RV32IF-NEXT: mv a1, a1
|
||||
; RV32IF-NEXT: xor a0, a0, a1
|
||||
; RV32IF-NEXT: ret
|
||||
%1 = fsub float -0.0, %a
|
||||
|
|
@ -96,6 +97,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
|
|||
; RV32IF-LABEL: fsgnjn_s:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: lui a2, 524288
|
||||
; RV32IF-NEXT: mv a2, a2
|
||||
; RV32IF-NEXT: xor a1, a1, a2
|
||||
; RV32IF-NEXT: fmv.w.x ft0, a1
|
||||
; RV32IF-NEXT: fmv.w.x ft1, a0
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ define i32 @pos_i32_hi20_only() nounwind {
|
|||
; RV32I-LABEL: pos_i32_hi20_only:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: lui a0, 16
|
||||
; RV32I-NEXT: mv a0, a0
|
||||
; RV32I-NEXT: ret
|
||||
ret i32 65536
|
||||
}
|
||||
|
|
@ -58,6 +59,7 @@ define i32 @neg_i32_hi20_only() nounwind {
|
|||
; RV32I-LABEL: neg_i32_hi20_only:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: lui a0, 1048560
|
||||
; RV32I-NEXT: mv a0, a0
|
||||
; RV32I-NEXT: ret
|
||||
ret i32 -65536
|
||||
}
|
||||
|
|
|
|||
|
|
@ -264,9 +264,10 @@ define void @va1_caller() nounwind {
|
|||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: addi sp, sp, -16
|
||||
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 261888
|
||||
; RV32I-FPELIM-NEXT: mv a3, a0
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
|
||||
; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
|
||||
; RV32I-FPELIM-NEXT: lui a3, 261888
|
||||
; RV32I-FPELIM-NEXT: addi a4, zero, 2
|
||||
; RV32I-FPELIM-NEXT: mv a2, zero
|
||||
; RV32I-FPELIM-NEXT: jalr a0
|
||||
|
|
@ -280,9 +281,10 @@ define void @va1_caller() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
|
||||
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||||
; RV32I-WITHFP-NEXT: lui a0, 261888
|
||||
; RV32I-WITHFP-NEXT: mv a3, a0
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
|
||||
; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
|
||||
; RV32I-WITHFP-NEXT: lui a3, 261888
|
||||
; RV32I-WITHFP-NEXT: addi a4, zero, 2
|
||||
; RV32I-WITHFP-NEXT: mv a2, zero
|
||||
; RV32I-WITHFP-NEXT: jalr a0
|
||||
|
|
@ -470,9 +472,10 @@ define void @va2_caller() nounwind {
|
|||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: addi sp, sp, -16
|
||||
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 261888
|
||||
; RV32I-FPELIM-NEXT: mv a3, a0
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
|
||||
; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
|
||||
; RV32I-FPELIM-NEXT: lui a3, 261888
|
||||
; RV32I-FPELIM-NEXT: mv a2, zero
|
||||
; RV32I-FPELIM-NEXT: jalr a0
|
||||
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
|
||||
|
|
@ -485,9 +488,10 @@ define void @va2_caller() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
|
||||
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||||
; RV32I-WITHFP-NEXT: lui a0, 261888
|
||||
; RV32I-WITHFP-NEXT: mv a3, a0
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
|
||||
; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
|
||||
; RV32I-WITHFP-NEXT: lui a3, 261888
|
||||
; RV32I-WITHFP-NEXT: mv a2, zero
|
||||
; RV32I-WITHFP-NEXT: jalr a0
|
||||
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
|
||||
|
|
@ -712,11 +716,13 @@ define void @va3_caller() nounwind {
|
|||
; RV32I-FPELIM: # %bb.0:
|
||||
; RV32I-FPELIM-NEXT: addi sp, sp, -16
|
||||
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 261888
|
||||
; RV32I-FPELIM-NEXT: mv a2, a0
|
||||
; RV32I-FPELIM-NEXT: lui a0, 262144
|
||||
; RV32I-FPELIM-NEXT: mv a5, a0
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
|
||||
; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 2
|
||||
; RV32I-FPELIM-NEXT: lui a2, 261888
|
||||
; RV32I-FPELIM-NEXT: lui a5, 262144
|
||||
; RV32I-FPELIM-NEXT: mv a1, zero
|
||||
; RV32I-FPELIM-NEXT: mv a4, zero
|
||||
; RV32I-FPELIM-NEXT: jalr a3
|
||||
|
|
@ -730,11 +736,13 @@ define void @va3_caller() nounwind {
|
|||
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
|
||||
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
|
||||
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||||
; RV32I-WITHFP-NEXT: lui a0, 261888
|
||||
; RV32I-WITHFP-NEXT: mv a2, a0
|
||||
; RV32I-WITHFP-NEXT: lui a0, 262144
|
||||
; RV32I-WITHFP-NEXT: mv a5, a0
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
|
||||
; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 2
|
||||
; RV32I-WITHFP-NEXT: lui a2, 261888
|
||||
; RV32I-WITHFP-NEXT: lui a5, 262144
|
||||
; RV32I-WITHFP-NEXT: mv a1, zero
|
||||
; RV32I-WITHFP-NEXT: mv a4, zero
|
||||
; RV32I-WITHFP-NEXT: jalr a3
|
||||
|
|
@ -1027,6 +1035,8 @@ define void @va5_aligned_stack_caller() nounwind {
|
|||
; RV32I-FPELIM-NEXT: lui a0, 335544
|
||||
; RV32I-FPELIM-NEXT: addi a0, a0, 1311
|
||||
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
|
||||
; RV32I-FPELIM-NEXT: lui a0, 688509
|
||||
; RV32I-FPELIM-NEXT: addi a6, a0, -2048
|
||||
; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee)
|
||||
; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
|
||||
; RV32I-FPELIM-NEXT: addi a0, zero, 1
|
||||
|
|
@ -1034,8 +1044,6 @@ define void @va5_aligned_stack_caller() nounwind {
|
|||
; RV32I-FPELIM-NEXT: addi a2, sp, 32
|
||||
; RV32I-FPELIM-NEXT: addi a3, zero, 12
|
||||
; RV32I-FPELIM-NEXT: addi a4, zero, 13
|
||||
; RV32I-FPELIM-NEXT: lui a6, 688509
|
||||
; RV32I-FPELIM-NEXT: addi a6, a6, -2048
|
||||
; RV32I-FPELIM-NEXT: addi a7, zero, 4
|
||||
; RV32I-FPELIM-NEXT: jalr a5
|
||||
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
|
||||
|
|
@ -1074,6 +1082,8 @@ define void @va5_aligned_stack_caller() nounwind {
|
|||
; RV32I-WITHFP-NEXT: lui a0, 335544
|
||||
; RV32I-WITHFP-NEXT: addi a0, a0, 1311
|
||||
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
|
||||
; RV32I-WITHFP-NEXT: lui a0, 688509
|
||||
; RV32I-WITHFP-NEXT: addi a6, a0, -2048
|
||||
; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee)
|
||||
; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
|
||||
; RV32I-WITHFP-NEXT: addi a0, zero, 1
|
||||
|
|
@ -1081,8 +1091,6 @@ define void @va5_aligned_stack_caller() nounwind {
|
|||
; RV32I-WITHFP-NEXT: addi a2, s0, -32
|
||||
; RV32I-WITHFP-NEXT: addi a3, zero, 12
|
||||
; RV32I-WITHFP-NEXT: addi a4, zero, 13
|
||||
; RV32I-WITHFP-NEXT: lui a6, 688509
|
||||
; RV32I-WITHFP-NEXT: addi a6, a6, -2048
|
||||
; RV32I-WITHFP-NEXT: addi a7, zero, 4
|
||||
; RV32I-WITHFP-NEXT: jalr a5
|
||||
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
|
||||
|
|
|
|||
|
|
@ -4,12 +4,5 @@
|
|||
# TODO ld
|
||||
# TODO sd
|
||||
|
||||
li x0, 4294967296 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
|
||||
li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
|
||||
li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
|
||||
|
||||
negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
|
||||
foo:
|
||||
.space 4
|
||||
|
|
|
|||
|
|
@ -1,71 +1,13 @@
|
|||
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-INST %s
|
||||
# RUN: llvm-mc %s -triple=riscv32 \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
|
||||
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
|
||||
# RUN: | llvm-objdump -riscv-no-aliases -d - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-INST %s
|
||||
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
|
||||
# RUN: | llvm-objdump -d - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
|
||||
|
||||
# The following check prefixes are used in this test:
|
||||
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
|
||||
# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
|
||||
# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
|
||||
|
||||
# CHECK-INST: addi a0, zero, 0
|
||||
# CHECK-ALIAS: mv a0, zero
|
||||
li x10, 0
|
||||
# CHECK-EXPAND: addi a0, zero, 1
|
||||
li x10, 1
|
||||
# CHECK-EXPAND: addi a0, zero, -1
|
||||
li x10, -1
|
||||
# CHECK-EXPAND: addi a0, zero, 2047
|
||||
li x10, 2047
|
||||
# CHECK-EXPAND: addi a0, zero, -2047
|
||||
li x10, -2047
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addi a1, a1, -2048
|
||||
li x11, 2048
|
||||
# CHECK-EXPAND: addi a1, zero, -2048
|
||||
li x11, -2048
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addi a1, a1, -2047
|
||||
li x11, 2049
|
||||
# CHECK-EXPAND: lui a1, 1048575
|
||||
# CHECK-EXPAND: addi a1, a1, 2047
|
||||
li x11, -2049
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addi a1, a1, -1
|
||||
li x11, 4095
|
||||
# CHECK-EXPAND: lui a1, 1048575
|
||||
# CHECK-EXPAND: addi a1, a1, 1
|
||||
li x11, -4095
|
||||
# CHECK-EXPAND: lui a2, 1
|
||||
li x12, 4096
|
||||
# CHECK-EXPAND: lui a2, 1048575
|
||||
li x12, -4096
|
||||
# CHECK-EXPAND: lui a2, 1
|
||||
# CHECK-EXPAND: addi a2, a2, 1
|
||||
li x12, 4097
|
||||
# CHECK-EXPAND: lui a2, 1048575
|
||||
# CHECK-EXPAND: addi a2, a2, -1
|
||||
li x12, -4097
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
# CHECK-EXPAND: addi a2, a2, -1
|
||||
li x12, 2147483647
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
# CHECK-EXPAND: addi a2, a2, 1
|
||||
li x12, -2147483647
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
li x12, -2147483648
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
li x12, 0x80000000
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
li x12, -0x80000000
|
||||
# CHECK-EXPAND: addi a2, zero, -1
|
||||
li x12, 0xFFFFFFFF
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
|
||||
|
||||
# CHECK-INST: csrrs t4, 3202, zero
|
||||
# CHECK-ALIAS: rdinstreth t4
|
||||
|
|
|
|||
|
|
@ -1,12 +1,6 @@
|
|||
# RUN: not llvm-mc %s -triple=riscv64 -riscv-no-aliases 2>&1 | FileCheck %s
|
||||
# RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck %s
|
||||
|
||||
li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
|
||||
li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
|
||||
|
||||
rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
|
||||
foo:
|
||||
.space 8
|
||||
|
|
|
|||
|
|
@ -1,100 +1,17 @@
|
|||
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
|
||||
# RUN: | FileCheck -check-prefix=CHECK-INST %s
|
||||
# RUN: llvm-mc %s -triple=riscv64 \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
|
||||
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
|
||||
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
|
||||
# RUN: | llvm-objdump -riscv-no-aliases -d - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
|
||||
# RUN: | FileCheck -check-prefix=CHECK-INST %s
|
||||
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
|
||||
# RUN: | llvm-objdump -d - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
|
||||
|
||||
# The following check prefixes are used in this test:
|
||||
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
|
||||
# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
|
||||
# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
|
||||
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
|
||||
|
||||
# TODO ld
|
||||
# TODO sd
|
||||
|
||||
# CHECK-INST: addiw a0, zero, 0
|
||||
# CHECK-ALIAS: sext.w a0, zero
|
||||
li x10, 0
|
||||
# CHECK-EXPAND: addiw a0, zero, 1
|
||||
li x10, 1
|
||||
# CHECK-EXPAND: addiw a0, zero, -1
|
||||
li x10, -1
|
||||
# CHECK-EXPAND: addiw a0, zero, 2047
|
||||
li x10, 2047
|
||||
# CHECK-EXPAND: addiw a0, zero, -2047
|
||||
li x10, -2047
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addiw a1, a1, -2048
|
||||
li x11, 2048
|
||||
# CHECK-EXPAND: addiw a1, zero, -2048
|
||||
li x11, -2048
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addiw a1, a1, -2047
|
||||
li x11, 2049
|
||||
# CHECK-EXPAND: lui a1, 1048575
|
||||
# CHECK-EXPAND: addiw a1, a1, 2047
|
||||
li x11, -2049
|
||||
# CHECK-EXPAND: lui a1, 1
|
||||
# CHECK-EXPAND: addiw a1, a1, -1
|
||||
li x11, 4095
|
||||
# CHECK-EXPAND: lui a1, 1048575
|
||||
# CHECK-EXPAND: addiw a1, a1, 1
|
||||
li x11, -4095
|
||||
# CHECK-EXPAND: lui a2, 1
|
||||
li x12, 4096
|
||||
# CHECK-EXPAND: lui a2, 1048575
|
||||
li x12, -4096
|
||||
# CHECK-EXPAND: lui a2, 1
|
||||
# CHECK-EXPAND: addiw a2, a2, 1
|
||||
li x12, 4097
|
||||
# CHECK-EXPAND: lui a2, 1048575
|
||||
# CHECK-EXPAND: addiw a2, a2, -1
|
||||
li x12, -4097
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
# CHECK-EXPAND: addiw a2, a2, -1
|
||||
li x12, 2147483647
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
# CHECK-EXPAND: addiw a2, a2, 1
|
||||
li x12, -2147483647
|
||||
# CHECK-EXPAND: lui a2, 524288
|
||||
li x12, -2147483648
|
||||
|
||||
# CHECK-EXPAND: addiw t0, zero, 1
|
||||
# CHECK-EXPAND: slli t0, t0, 32
|
||||
li t0, 0x100000000
|
||||
# CHECK-EXPAND: addiw t1, zero, -1
|
||||
# CHECK-EXPAND: slli t1, t1, 63
|
||||
li t1, 0x8000000000000000
|
||||
# CHECK-EXPAND: addiw t1, zero, -1
|
||||
# CHECK-EXPAND: slli t1, t1, 63
|
||||
li t1, -0x8000000000000000
|
||||
# CHECK-EXPAND: lui t2, 9321
|
||||
# CHECK-EXPAND: addiw t2, t2, -1329
|
||||
# CHECK-EXPAND: slli t2, t2, 35
|
||||
li t2, 0x1234567800000000
|
||||
# CHECK-EXPAND: addiw t3, zero, 7
|
||||
# CHECK-EXPAND: slli t3, t3, 36
|
||||
# CHECK-EXPAND: addi t3, t3, 11
|
||||
# CHECK-EXPAND: slli t3, t3, 24
|
||||
# CHECK-EXPAND: addi t3, t3, 15
|
||||
li t3, 0x700000000B00000F
|
||||
# CHECK-EXPAND: lui t4, 583
|
||||
# CHECK-EXPAND: addiw t4, t4, -1875
|
||||
# CHECK-EXPAND: slli t4, t4, 14
|
||||
# CHECK-EXPAND: addi t4, t4, -947
|
||||
# CHECK-EXPAND: slli t4, t4, 12
|
||||
# CHECK-EXPAND: addi t4, t4, 1511
|
||||
# CHECK-EXPAND: slli t4, t4, 13
|
||||
# CHECK-EXPAND: addi t4, t4, -272
|
||||
li t4, 0x123456789abcdef0
|
||||
# CHECK-EXPAND: addiw t5, zero, -1
|
||||
li t5, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
# CHECK-INST: subw t6, zero, ra
|
||||
# CHECK-ALIAS: negw t6, ra
|
||||
negw x31, x1
|
||||
|
|
|
|||
|
|
@ -19,10 +19,6 @@
|
|||
# RUN: | llvm-objdump -d - \
|
||||
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
|
||||
|
||||
# The following check prefixes are used in this test:
|
||||
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
|
||||
# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
|
||||
|
||||
# TODO la
|
||||
# TODO lb lh lw
|
||||
# TODO sb sh sw
|
||||
|
|
@ -30,6 +26,7 @@
|
|||
# CHECK-INST: addi zero, zero, 0
|
||||
# CHECK-ALIAS: nop
|
||||
nop
|
||||
# TODO li
|
||||
# CHECK-INST: addi t6, zero, 0
|
||||
# CHECK-ALIAS: mv t6, zero
|
||||
mv x31, zero
|
||||
|
|
|
|||
Loading…
Reference in New Issue