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AMDGPU: Implement getLoadStoreVecRegBitWidth 

llvm-svn: 274312
This commit is contained in:
Matt Arsenault 2016-07-01 00:56:27 +00:00
parent 286d94884b
commit 0994bd57fb
2 changed files with 23 additions and 0 deletions
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22
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
View File

@ -80,6 +80,28 @@ unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
return Vector ? 0 : 32; return Vector ? 0 : 32;
} }
unsigned AMDGPUTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) {
switch (AddrSpace) {
case AMDGPUAS::GLOBAL_ADDRESS:
case AMDGPUAS::CONSTANT_ADDRESS:
case AMDGPUAS::FLAT_ADDRESS:
return 128;
case AMDGPUAS::LOCAL_ADDRESS:
case AMDGPUAS::REGION_ADDRESS:
return 64;
case AMDGPUAS::PRIVATE_ADDRESS:
return 8 * ST->getMaxPrivateElementSize();
default:
if (ST->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS &&
(AddrSpace == AMDGPUAS::PARAM_D_ADDRESS ||
AddrSpace == AMDGPUAS::PARAM_I_ADDRESS ||
(AddrSpace >= AMDGPUAS::CONSTANT_BUFFER_0 &&
AddrSpace <= AMDGPUAS::CONSTANT_BUFFER_15)))
return 128;
llvm_unreachable("unhandled address space");
}
}
unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) { unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
// Semi-arbitrary large amount. // Semi-arbitrary large amount.
return 64; return 64;

1
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
View File

@ -82,6 +82,7 @@ public:
unsigned getNumberOfRegisters(bool Vector); unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector); unsigned getRegisterBitWidth(bool Vector);
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace);
unsigned getMaxInterleaveFactor(unsigned VF); unsigned getMaxInterleaveFactor(unsigned VF);
int getArithmeticInstrCost( int getArithmeticInstrCost(