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Codegen shufflevector as VVECTOR_SHUFFLE 

llvm-svn: 27529
This commit is contained in:
Chris Lattner 2006-04-08 04:15:24 +00:00
parent 101ea66813
commit 098c01e94e
2 changed files with 25 additions and 2 deletions
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13
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1447,6 +1447,12 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
AddToWorkList(XORNode.Val);
return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
}
// Simplify the expression using non-local knowledge.
if (!MVT::isVector(VT) &&
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
return SDOperand();
}
@ -2044,8 +2050,10 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
// type, convert each element. This handles FP<->INT cases.
if (SrcBitSize == DstBitSize) {
std::vector<SDOperand> Ops;
for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i)
for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
AddToWorkList(Ops.back().Val);
}
Ops.push_back(*(BV->op_end()-2)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT));
return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
@ -2635,6 +2643,7 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
UnOps.push_back(NumElts);
UnOps.push_back(EltType);
Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
AddToWorkList(Ops.back().Val);
}
Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
Ops.push_back(NumElts);
@ -2690,6 +2699,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
}
ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
MappedOps);
AddToWorkList(ShufMask.Val);
return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
N->getOperand(0),
DAG.getNode(ISD::UNDEF, N->getValueType(0)),
@ -2755,6 +2765,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
RHSOp.getOpcode() != ISD::ConstantFP))
break;
Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
AddToWorkList(Ops.back().Val);
assert((Ops.back().getOpcode() == ISD::UNDEF ||
Ops.back().getOpcode() == ISD::Constant ||
Ops.back().getOpcode() == ISD::ConstantFP) &&

14
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -516,7 +516,7 @@ public:
void visitExtractElement(User &I);
void visitInsertElement(User &I);
void visitShuffleVector(User &I) { assert(0 && "ShuffleVector not impl!"); }
void visitShuffleVector(User &I);
void visitGetElementPtr(User &I);
void visitCast(User &I);
@ -1076,6 +1076,18 @@ void SelectionDAGLowering::visitExtractElement(User &I) {
TLI.getValueType(I.getType()), InVec, InIdx));
}
void SelectionDAGLowering::visitShuffleVector(User &I) {
SDOperand V1 = getValue(I.getOperand(0));
SDOperand V2 = getValue(I.getOperand(1));
SDOperand Mask = getValue(I.getOperand(2));
SDOperand Num = *(V1.Val->op_end()-2);
SDOperand Typ = *(V2.Val->op_end()-1);
setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
V1, V2, Mask, Num, Typ));
}
void SelectionDAGLowering::visitGetElementPtr(User &I) {
SDOperand N = getValue(I.getOperand(0));
const Type *Ty = I.getOperand(0)->getType();