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[Test][AggressiveInstCombine] Add one more test for shift truncation 

Add test for which `OrigBitWidth != SrcBitWidth`
(https://reviews.llvm.org/D108091#2950131)
This commit is contained in:
Anton Afanasyev 2021-08-18 09:09:05 +03:00
parent 5aa0f9cc9a
commit 0988488ed4
1 changed files with 30 additions and 0 deletions
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30
llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
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@ -92,6 +92,36 @@ define i32 @shl_check_no_overflow(i32 %call62, i16 %call63) {
ret i32 %conv68
}
define i16 @shl_smaller_bitwidth(i8 %x) {
; CHECK-LABEL: @shl_smaller_bitwidth(
; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 1
; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], 42
; CHECK-NEXT: ret i16 [[AND]]
;
%zext = zext i8 %x to i16
%shl = shl i16 %zext, 1
%zext2 = zext i16 %shl to i32
%and = and i32 %zext2, 42
%trunc = trunc i32 %and to i16
ret i16 %trunc
}
define i16 @shl_larger_bitwidth(i8 %x) {
; CHECK-LABEL: @shl_larger_bitwidth(
; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 1
; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], 42
; CHECK-NEXT: ret i16 [[AND]]
;
%zext = zext i8 %x to i64
%shl = shl i64 %zext, 1
%zext2 = trunc i64 %shl to i32
%and = and i32 %zext2, 42
%trunc = trunc i32 %and to i16
ret i16 %trunc
}
define <2 x i16> @shl_vector(<2 x i8> %x) {
; CHECK-LABEL: @shl_vector(
; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>