forked from OSchip/llvm-project
[RISCV] Add isel patterns for SH*ADD(.UW)
This adds an initial set of patterns for these instructions. Its more complicated that I would like for the sh*add.uw instructions because there is no guaranteed canonicalization for shl/and with constants. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D95106
This commit is contained in:
Craig Topper
parent
99a0aa07e9
commit
095e245e16
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@ -921,6 +921,15 @@ def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)),
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(SHFLI GPR:$rs1, (i64 1))>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZba] in {
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def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), GPR:$rs2),
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(SH1ADD GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), GPR:$rs2),
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(SH2ADD GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
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(SH3ADD GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtZba]
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let Predicates = [HasStdExtZba, IsRV64] in {
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def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
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(SLLIUW GPR:$rs1, uimm5:$shamt)>;
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@ -929,7 +938,21 @@ def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
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def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
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(ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(and GPR:$rs, 0x00000000FFFFFFFF), (ADDUW GPR:$rs, X0)>;
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}
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def : Pat<(add (shl (and GPR:$rs1, (i64 0xFFFFFFFF)), (XLenVT 1)), GPR:$rs2),
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(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (shl (and GPR:$rs1, (i64 0xFFFFFFFF)), (XLenVT 2)), GPR:$rs2),
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(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (shl (and GPR:$rs1, (i64 0xFFFFFFFF)), (XLenVT 3)), GPR:$rs2),
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(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 1)), GPR:$rs2),
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(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 2)), GPR:$rs2),
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(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 3)), GPR:$rs2),
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(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtZba, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
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@ -0,0 +1,82 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IB
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IBA
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define signext i16 @sh1add(i64 %0, i16* %1) {
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; RV32I-LABEL: sh1add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 1
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; RV32I-NEXT: add a0, a2, a0
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; RV32I-NEXT: lh a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: sh1add:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: sh1add a0, a0, a2
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; RV32IB-NEXT: lh a0, 0(a0)
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; RV32IB-NEXT: ret
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;
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; RV32IBA-LABEL: sh1add:
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; RV32IBA: # %bb.0:
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; RV32IBA-NEXT: sh1add a0, a0, a2
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; RV32IBA-NEXT: lh a0, 0(a0)
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; RV32IBA-NEXT: ret
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%3 = getelementptr inbounds i16, i16* %1, i64 %0
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%4 = load i16, i16* %3
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ret i16 %4
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}
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define i32 @sh2add(i64 %0, i32* %1) {
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; RV32I-LABEL: sh2add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 2
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; RV32I-NEXT: add a0, a2, a0
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: sh2add:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: sh2add a0, a0, a2
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; RV32IB-NEXT: lw a0, 0(a0)
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; RV32IB-NEXT: ret
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;
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; RV32IBA-LABEL: sh2add:
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; RV32IBA: # %bb.0:
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; RV32IBA-NEXT: sh2add a0, a0, a2
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; RV32IBA-NEXT: lw a0, 0(a0)
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; RV32IBA-NEXT: ret
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%3 = getelementptr inbounds i32, i32* %1, i64 %0
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%4 = load i32, i32* %3
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ret i32 %4
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}
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define i64 @sh3add(i64 %0, i64* %1) {
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; RV32I-LABEL: sh3add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 3
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; RV32I-NEXT: add a1, a2, a0
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: sh3add:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: sh3add a1, a0, a2
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; RV32IB-NEXT: lw a0, 0(a1)
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; RV32IB-NEXT: lw a1, 4(a1)
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; RV32IB-NEXT: ret
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;
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; RV32IBA-LABEL: sh3add:
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; RV32IBA: # %bb.0:
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; RV32IBA-NEXT: sh3add a1, a0, a2
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; RV32IBA-NEXT: lw a0, 0(a1)
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; RV32IBA-NEXT: lw a1, 4(a1)
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; RV32IBA-NEXT: ret
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%3 = getelementptr inbounds i64, i64* %1, i64 %0
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%4 = load i64, i64* %3
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ret i64 %4
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}
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@ -129,3 +129,234 @@ define i64 @zextw_i64(i64 %a) nounwind {
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%and = and i64 %a, 4294967295
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ret i64 %and
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}
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define signext i16 @sh1add(i64 %0, i16* %1) {
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; RV64I-LABEL: sh1add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 1
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lh a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add a0, a0, a1
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; RV64IB-NEXT: lh a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add a0, a0, a1
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; RV64IBA-NEXT: lh a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i16, i16* %1, i64 %0
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%4 = load i16, i16* %3
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ret i16 %4
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}
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define signext i32 @sh2add(i64 %0, i32* %1) {
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; RV64I-LABEL: sh2add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add a0, a0, a1
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add a0, a0, a1
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; RV64IBA-NEXT: lw a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i32, i32* %1, i64 %0
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%4 = load i32, i32* %3
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ret i32 %4
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}
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define i64 @sh3add(i64 %0, i64* %1) {
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; RV64I-LABEL: sh3add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ld a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add a0, a0, a1
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; RV64IB-NEXT: ld a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add a0, a0, a1
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; RV64IBA-NEXT: ld a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i64, i64* %1, i64 %0
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%4 = load i64, i64* %3
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ret i64 %4
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}
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define signext i16 @sh1adduw(i32 signext %0, i16* %1) {
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; RV64I-LABEL: sh1adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a0, a0, 1
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lh a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add.uw a0, a0, a1
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; RV64IB-NEXT: lh a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add.uw a0, a0, a1
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; RV64IBA-NEXT: lh a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i16, i16* %1, i64 %3
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%5 = load i16, i16* %4
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ret i16 %5
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}
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define i64 @sh1adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh1adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 1
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 33
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; RV64I-NEXT: addi a2, a2, -2
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 1
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%4 = and i64 %3, 8589934590
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%5 = add i64 %4, %1
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ret i64 %5
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}
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define signext i32 @sh2adduw(i32 signext %0, i32* %1) {
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; RV64I-LABEL: sh2adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add.uw a0, a0, a1
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add.uw a0, a0, a1
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; RV64IBA-NEXT: lw a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i32, i32* %1, i64 %3
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%5 = load i32, i32* %4
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ret i32 %5
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}
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define i64 @sh2adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh2adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 34
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; RV64I-NEXT: addi a2, a2, -4
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 2
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%4 = and i64 %3, 17179869180
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%5 = add i64 %4, %1
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ret i64 %5
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}
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define i64 @sh3adduw(i32 signext %0, i64* %1) {
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; RV64I-LABEL: sh3adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ld a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add.uw a0, a0, a1
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; RV64IB-NEXT: ld a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add.uw a0, a0, a1
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; RV64IBA-NEXT: ld a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i64, i64* %1, i64 %3
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%5 = load i64, i64* %4
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ret i64 %5
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}
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define i64 @sh3adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh3adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 35
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; RV64I-NEXT: addi a2, a2, -8
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 3
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%4 = and i64 %3, 34359738360
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%5 = add i64 %4, %1
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ret i64 %5
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}
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