forked from OSchip/llvm-project
[RISCV][NFC] Add tests for folds of ADDIs into load/stores
This patch adds tests for folds of ADDIs into load/stores, focusing on load/stores with nonzero offsets. When the offset is nonzero we currently don't do the fold. A follow-up patch will improve on that. Differential Revision: https://reviews.llvm.org/D79689
This commit is contained in:
Luís Marques
parent
84f3805805
commit
0947a8ca98
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; We can often fold an ADDI into the offset of load/store instructions:
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; (load (addi base, off1), off2) -> (load base, off1+off2)
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; (store val, (addi base, off1), off2) -> (store val, base, off1+off2)
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; This is possible when the off1+off2 continues to fit the 12-bit immediate.
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; Check if we do the fold under various conditions. If off1 is (the low part of)
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; an address the fold's safety depends on the variable's alignment.
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@g_0 = global i64 0
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@g_1 = global i64 0, align 1
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@g_2 = global i64 0, align 2
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@g_4 = global i64 0, align 4
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@g_8 = global i64 0, align 8
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@g_16 = global i64 0, align 16
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define i64 @load_g_0() nounwind {
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; RV32I-LABEL: load_g_0:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_0)
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; RV32I-NEXT: lw a0, %lo(g_0)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_0)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_0:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_0)
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; RV64I-NEXT: ld a0, %lo(g_0)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_0
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ret i64 %0
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}
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define i64 @load_g_1() nounwind {
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; RV32I-LABEL: load_g_1:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_1)
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; RV32I-NEXT: lw a0, %lo(g_1)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_1)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_1:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_1)
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; RV64I-NEXT: ld a0, %lo(g_1)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_1
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ret i64 %0
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}
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define i64 @load_g_2() nounwind {
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; RV32I-LABEL: load_g_2:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_2)
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; RV32I-NEXT: lw a0, %lo(g_2)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_2)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_2:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_2)
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; RV64I-NEXT: ld a0, %lo(g_2)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_2
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ret i64 %0
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}
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define i64 @load_g_4() nounwind {
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; RV32I-LABEL: load_g_4:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_4)
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; RV32I-NEXT: lw a0, %lo(g_4)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_4)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_4:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_4)
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; RV64I-NEXT: ld a0, %lo(g_4)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_4
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ret i64 %0
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}
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define i64 @load_g_8() nounwind {
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; RV32I-LABEL: load_g_8:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_8)
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; RV32I-NEXT: lw a0, %lo(g_8)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_8)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_8:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_8)
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; RV64I-NEXT: ld a0, %lo(g_8)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_8
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ret i64 %0
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}
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define i64 @load_g_16() nounwind {
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; RV32I-LABEL: load_g_16:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, %hi(g_16)
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; RV32I-NEXT: lw a0, %lo(g_16)(a1)
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; RV32I-NEXT: addi a1, a1, %lo(g_16)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_g_16:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_16)
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; RV64I-NEXT: ld a0, %lo(g_16)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @g_16
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ret i64 %0
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}
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define void @store_g_4() nounwind {
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; RV32I-LABEL: store_g_4:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %hi(g_4)
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; RV32I-NEXT: sw zero, %lo(g_4)(a0)
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; RV32I-NEXT: addi a0, a0, %lo(g_4)
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; RV32I-NEXT: sw zero, 4(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_g_4:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_4)
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; RV64I-NEXT: sd zero, %lo(g_4)(a0)
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; RV64I-NEXT: ret
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entry:
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store i64 0, i64* @g_4
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ret void
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}
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define void @store_g_8() nounwind {
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; RV32I-LABEL: store_g_8:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %hi(g_8)
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; RV32I-NEXT: sw zero, %lo(g_8)(a0)
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; RV32I-NEXT: addi a0, a0, %lo(g_8)
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; RV32I-NEXT: sw zero, 4(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_g_8:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(g_8)
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; RV64I-NEXT: sd zero, %lo(g_8)(a0)
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; RV64I-NEXT: ret
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entry:
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store i64 0, i64* @g_8
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ret void
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}
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; Check for folds in accesses to the second element of an i64 array.
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@ga_8 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 8
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@ga_16 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 16
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define i64 @load_ga_8() nounwind {
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; RV32I-LABEL: load_ga_8:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %hi(ga_8)
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; RV32I-NEXT: addi a1, a0, %lo(ga_8)
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; RV32I-NEXT: lw a0, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_ga_8:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(ga_8+8)
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; RV64I-NEXT: ld a0, %lo(ga_8+8)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_8, i32 0, i32 1)
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ret i64 %0
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}
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define i64 @load_ga_16() nounwind {
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; RV32I-LABEL: load_ga_16:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %hi(ga_16)
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; RV32I-NEXT: addi a1, a0, %lo(ga_16)
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; RV32I-NEXT: lw a0, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_ga_16:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %hi(ga_16+8)
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; RV64I-NEXT: ld a0, %lo(ga_16+8)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @ga_16, i32 0, i32 1)
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ret i64 %0
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}
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; Check for folds in accesses to thread-local variables.
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@tl_4 = thread_local global i64 0, align 4
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@tl_8 = thread_local global i64 0, align 8
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define i64 @load_tl_4() nounwind {
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; RV32I-LABEL: load_tl_4:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %tprel_hi(tl_4)
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; RV32I-NEXT: add a1, a0, tp, %tprel_add(tl_4)
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; RV32I-NEXT: lw a0, %tprel_lo(tl_4)(a1)
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; RV32I-NEXT: addi a1, a1, %tprel_lo(tl_4)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_tl_4:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %tprel_hi(tl_4)
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; RV64I-NEXT: add a0, a0, tp, %tprel_add(tl_4)
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; RV64I-NEXT: ld a0, %tprel_lo(tl_4)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @tl_4
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ret i64 %0
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}
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define i64 @load_tl_8() nounwind {
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; RV32I-LABEL: load_tl_8:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, %tprel_hi(tl_8)
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; RV32I-NEXT: add a1, a0, tp, %tprel_add(tl_8)
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; RV32I-NEXT: lw a0, %tprel_lo(tl_8)(a1)
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; RV32I-NEXT: addi a1, a1, %tprel_lo(tl_8)
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; RV32I-NEXT: lw a1, 4(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_tl_8:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: lui a0, %tprel_hi(tl_8)
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; RV64I-NEXT: add a0, a0, tp, %tprel_add(tl_8)
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; RV64I-NEXT: ld a0, %tprel_lo(tl_8)(a0)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* @tl_8
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ret i64 %0
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}
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define i64 @load_const_ok() nounwind {
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; RV32I-LABEL: load_const_ok:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lw a0, 2040(zero)
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; RV32I-NEXT: lw a1, 2044(zero)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_const_ok:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: ld a0, 2040(zero)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* inttoptr (i32 2040 to i64*)
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ret i64 %0
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}
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define i64 @load_cost_overflow() nounwind {
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; RV32I-LABEL: load_cost_overflow:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: lw a1, -2048(a0)
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; RV32I-NEXT: lw a0, 2044(zero)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_cost_overflow:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: ld a0, 2044(zero)
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; RV64I-NEXT: ret
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entry:
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%0 = load i64, i64* inttoptr (i64 2044 to i64*)
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ret i64 %0
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}
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