forked from OSchip/llvm-project
[PowerPC] Implement Vector Insert Builtins in LLVM/Clang
Implements vec_insertl() and vec_inserth(). Differential Revision: https://reviews.llvm.org/D82365
This commit is contained in:
Biplob Mishra
Lei Huang
parent
551092bc3d
commit
0939e04e41
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@ -320,6 +320,22 @@ BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
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BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
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BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
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// P10 Vector Insert built-ins.
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BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
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BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
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BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
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BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
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BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
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BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
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BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
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BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
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BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
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BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "")
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BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "")
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BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "")
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BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
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BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
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// VSX built-ins.
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BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
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@ -16889,6 +16889,136 @@ vec_cnttzm(vector unsigned long long __a, vector unsigned long long __b) {
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#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
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/* vec_insertl */
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static __inline__ vector unsigned char __ATTRS_o_ai
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vec_insertl(unsigned char __a, vector unsigned char __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsbrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsblx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned short __ATTRS_o_ai
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vec_insertl(unsigned short __a, vector unsigned short __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinshrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinshlx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_insertl(unsigned int __a, vector unsigned int __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinswrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinswlx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned long long __ATTRS_o_ai vec_insertl(
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unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsdrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsdlx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned char __ATTRS_o_ai vec_insertl(
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vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsbvrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsbvlx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned short __ATTRS_o_ai vec_insertl(
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vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinshvrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinshvlx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned int __ATTRS_o_ai vec_insertl(
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vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinswvrx(__b, __c, __a);
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#else
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return __builtin_altivec_vinswvlx(__b, __c, __a);
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#endif
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}
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/* vec_inserth */
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static __inline__ vector unsigned char __ATTRS_o_ai
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vec_inserth(unsigned char __a, vector unsigned char __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsblx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsbrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned short __ATTRS_o_ai
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vec_inserth(unsigned short __a, vector unsigned short __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinshlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinshrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_inserth(unsigned int __a, vector unsigned int __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinswlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinswrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned long long __ATTRS_o_ai vec_inserth(
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unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsdlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsdrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned char __ATTRS_o_ai vec_inserth(
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vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinsbvlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinsbvrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned short __ATTRS_o_ai vec_inserth(
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vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinshvlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinshvrx(__b, __c, __a);
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#endif
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}
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static __inline__ vector unsigned int __ATTRS_o_ai vec_inserth(
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vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_altivec_vinswvlx(__b, __c, __a);
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#else
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return __builtin_altivec_vinswvrx(__b, __c, __a);
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#endif
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}
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#ifdef __VSX__
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/* vec_permx */
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@ -3,6 +3,14 @@
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// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
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// RUN: -o - | FileCheck %s
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// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
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// RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
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// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE
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// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
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// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
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// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE
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#include <altivec.h>
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vector signed char vsca, vscb;
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@ -16,7 +24,10 @@ vector unsigned long long vulla, vullb, vullc;
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vector unsigned __int128 vui128a, vui128b, vui128c;
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vector float vfa, vfb;
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vector double vda, vdb;
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unsigned int uia;
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unsigned int uia, uib;
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unsigned char uca;
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unsigned short usa;
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unsigned long long ulla;
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vector unsigned long long test_vpdepd(void) {
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// CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
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@ -389,3 +400,115 @@ vector double test_vec_blend_d(void) {
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// CHECK-NEXT: ret <2 x double>
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return vec_blendv(vda, vdb, vullc);
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}
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vector unsigned char test_vec_insertl_uc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_insertl(uca, vuca, uia);
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}
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vector unsigned short test_vec_insertl_us(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <8 x i16>
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// CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <8 x i16>
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return vec_insertl(usa, vusa, uia);
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}
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vector unsigned int test_vec_insertl_ui(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <4 x i32>
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// CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <4 x i32>
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return vec_insertl(uib, vuia, uia);
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}
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vector unsigned long long test_vec_insertl_ul(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <2 x i64>
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// CHECK-LE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <2 x i64>
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return vec_insertl(ulla, vulla, uia);
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}
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vector unsigned char test_vec_insertl_ucv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_insertl(vuca, vucb, uia);
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}
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vector unsigned short test_vec_insertl_usv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
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// CHECK-BE-NEXT: ret <8 x i16>
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// CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
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// CHECK-LE-NEXT: ret <8 x i16>
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return vec_insertl(vusa, vusb, uia);
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}
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vector unsigned int test_vec_insertl_uiv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
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// CHECK-BE-NEXT: ret <4 x i32>
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// CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
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// CHECK-LE-NEXT: ret <4 x i32>
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return vec_insertl(vuia, vuib, uia);
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}
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vector unsigned char test_vec_inserth_uc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_inserth(uca, vuca, uia);
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}
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vector unsigned short test_vec_inserth_us(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <8 x i16>
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// CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <8 x i16>
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return vec_inserth(usa, vusa, uia);
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}
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vector unsigned int test_vec_inserth_ui(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <4 x i32>
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// CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <4 x i32>
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return vec_inserth(uib, vuia, uia);
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}
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vector unsigned long long test_vec_inserth_ul(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-BE-NEXT: ret <2 x i64>
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// CHECK-LE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
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// CHECK-LE-NEXT: ret <2 x i64>
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return vec_inserth(ulla, vulla, uia);
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}
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vector unsigned char test_vec_inserth_ucv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_inserth(vuca, vucb, uia);
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}
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vector unsigned short test_vec_inserth_usv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
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// CHECK-BE-NEXT: ret <8 x i16>
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// CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
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// CHECK-LE-NEXT: ret <8 x i16>
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return vec_inserth(vusa, vusb, uia);
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}
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vector unsigned int test_vec_inserth_uiv(void) {
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// CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
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// CHECK-BE-NEXT: ret <4 x i32>
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// CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
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// CHECK-LE-NEXT: ret <4 x i32>
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return vec_inserth(vuia, vuib, uia);
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}
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@ -464,6 +464,64 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<2>>]>;
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// P10 Vector Insert.
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def int_ppc_altivec_vinsblx : GCCBuiltin<"__builtin_altivec_vinsblx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinsbrx : GCCBuiltin<"__builtin_altivec_vinsbrx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshlx : GCCBuiltin<"__builtin_altivec_vinshlx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshrx : GCCBuiltin<"__builtin_altivec_vinshrx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswlx : GCCBuiltin<"__builtin_altivec_vinswlx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswrx : GCCBuiltin<"__builtin_altivec_vinswrx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinsdlx : GCCBuiltin<"__builtin_altivec_vinsdlx">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2i64_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrNoMem]>;
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||||
def int_ppc_altivec_vinsdrx : GCCBuiltin<"__builtin_altivec_vinsdrx">,
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v2i64_ty, llvm_i64_ty, llvm_i64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinsbvlx : GCCBuiltin<"__builtin_altivec_vinsbvlx">,
|
||||
Intrinsic<[llvm_v16i8_ty],
|
||||
[llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinsbvrx : GCCBuiltin<"__builtin_altivec_vinsbvrx">,
|
||||
Intrinsic<[llvm_v16i8_ty],
|
||||
[llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinshvlx : GCCBuiltin<"__builtin_altivec_vinshvlx">,
|
||||
Intrinsic<[llvm_v8i16_ty],
|
||||
[llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
|
||||
Intrinsic<[llvm_v8i16_ty],
|
||||
[llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
|
||||
Intrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
|
||||
Intrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
|
||||
[IntrNoMem]>;
|
||||
}
|
||||
|
||||
// Vector average.
|
||||
|
|
|
|||
|
|
@ -777,20 +777,77 @@ let Predicates = [IsISA3_1] in {
|
|||
i32:$SH))]>;
|
||||
def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>;
|
||||
def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>;
|
||||
def VINSBVLX : VXForm_VTB5_RA5_ins<15, "vinsbvlx", []>;
|
||||
def VINSBVRX : VXForm_VTB5_RA5_ins<271, "vinsbvrx", []>;
|
||||
def VINSHVLX : VXForm_VTB5_RA5_ins<79, "vinshvlx", []>;
|
||||
def VINSHVRX : VXForm_VTB5_RA5_ins<335, "vinshvrx", []>;
|
||||
def VINSWVLX : VXForm_VTB5_RA5_ins<143, "vinswvlx", []>;
|
||||
def VINSWVRX : VXForm_VTB5_RA5_ins<399, "vinswvrx", []>;
|
||||
def VINSBLX : VXForm_VRT5_RAB5_ins<527, "vinsblx", []>;
|
||||
def VINSBRX : VXForm_VRT5_RAB5_ins<783, "vinsbrx", []>;
|
||||
def VINSHLX : VXForm_VRT5_RAB5_ins<591, "vinshlx", []>;
|
||||
def VINSHRX : VXForm_VRT5_RAB5_ins<847, "vinshrx", []>;
|
||||
def VINSWLX : VXForm_VRT5_RAB5_ins<655, "vinswlx", []>;
|
||||
def VINSWRX : VXForm_VRT5_RAB5_ins<911, "vinswrx", []>;
|
||||
def VINSDLX : VXForm_VRT5_RAB5_ins<719, "vinsdlx", []>;
|
||||
def VINSDRX : VXForm_VRT5_RAB5_ins<975, "vinsdrx", []>;
|
||||
def VINSBVLX :
|
||||
VXForm_VTB5_RA5_ins<15, "vinsbvlx",
|
||||
[(set v16i8:$vD,
|
||||
(int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA,
|
||||
v16i8:$vB))]>;
|
||||
def VINSBVRX :
|
||||
VXForm_VTB5_RA5_ins<271, "vinsbvrx",
|
||||
[(set v16i8:$vD,
|
||||
(int_ppc_altivec_vinsbvrx v16i8:$vDi, i64:$rA,
|
||||
v16i8:$vB))]>;
|
||||
def VINSHVLX :
|
||||
VXForm_VTB5_RA5_ins<79, "vinshvlx",
|
||||
[(set v8i16:$vD,
|
||||
(int_ppc_altivec_vinshvlx v8i16:$vDi, i64:$rA,
|
||||
v8i16:$vB))]>;
|
||||
def VINSHVRX :
|
||||
VXForm_VTB5_RA5_ins<335, "vinshvrx",
|
||||
[(set v8i16:$vD,
|
||||
(int_ppc_altivec_vinshvrx v8i16:$vDi, i64:$rA,
|
||||
v8i16:$vB))]>;
|
||||
def VINSWVLX :
|
||||
VXForm_VTB5_RA5_ins<143, "vinswvlx",
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vinswvlx v4i32:$vDi, i64:$rA,
|
||||
v4i32:$vB))]>;
|
||||
def VINSWVRX :
|
||||
VXForm_VTB5_RA5_ins<399, "vinswvrx",
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vinswvrx v4i32:$vDi, i64:$rA,
|
||||
v4i32:$vB))]>;
|
||||
def VINSBLX :
|
||||
VXForm_VRT5_RAB5_ins<527, "vinsblx",
|
||||
[(set v16i8:$vD,
|
||||
(int_ppc_altivec_vinsblx v16i8:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSBRX :
|
||||
VXForm_VRT5_RAB5_ins<783, "vinsbrx",
|
||||
[(set v16i8:$vD,
|
||||
(int_ppc_altivec_vinsbrx v16i8:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSHLX :
|
||||
VXForm_VRT5_RAB5_ins<591, "vinshlx",
|
||||
[(set v8i16:$vD,
|
||||
(int_ppc_altivec_vinshlx v8i16:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSHRX :
|
||||
VXForm_VRT5_RAB5_ins<847, "vinshrx",
|
||||
[(set v8i16:$vD,
|
||||
(int_ppc_altivec_vinshrx v8i16:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSWLX :
|
||||
VXForm_VRT5_RAB5_ins<655, "vinswlx",
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vinswlx v4i32:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSWRX :
|
||||
VXForm_VRT5_RAB5_ins<911, "vinswrx",
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vinswrx v4i32:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSDLX :
|
||||
VXForm_VRT5_RAB5_ins<719, "vinsdlx",
|
||||
[(set v2i64:$vD,
|
||||
(int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
def VINSDRX :
|
||||
VXForm_VRT5_RAB5_ins<975, "vinsdrx",
|
||||
[(set v2i64:$vD,
|
||||
(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA,
|
||||
i64:$rB))]>;
|
||||
|
||||
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
|
||||
[(set v2i64:$vD,
|
||||
|
|
|
|||
|
|
@ -81,3 +81,153 @@ entry:
|
|||
ret <2 x i64> %0
|
||||
}
|
||||
declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
|
||||
|
||||
define <16 x i8> @testVINSBLX(<16 x i8> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSBLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsblx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i64 %b, i64 %c)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i64, i64)
|
||||
|
||||
define <16 x i8> @testVINSBRX(<16 x i8> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSBRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsbrx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i64 %b, i64 %c)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i64, i64)
|
||||
|
||||
define <8 x i16> @testVINSHLX(<8 x i16> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSHLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinshlx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i64 %b, i64 %c)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i64, i64)
|
||||
|
||||
define <8 x i16> @testVINSHRX(<8 x i16> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSHRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinshrx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i64 %b, i64 %c)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i64, i64)
|
||||
|
||||
define <4 x i32> @testVINSWLX(<4 x i32> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSWLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinswlx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i64 %b, i64 %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i64, i64)
|
||||
|
||||
define <4 x i32> @testVINSWRX(<4 x i32> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSWRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinswrx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i64 %b, i64 %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i64, i64)
|
||||
|
||||
define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSDLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsdlx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64> %a, i64 %b, i64 %c)
|
||||
ret <2 x i64> %0
|
||||
}
|
||||
declare <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64>, i64, i64)
|
||||
|
||||
define <2 x i64> @testVINSDRX(<2 x i64> %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: testVINSDRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsdrx v2, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64> %a, i64 %b, i64 %c)
|
||||
ret <2 x i64> %0
|
||||
}
|
||||
declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64)
|
||||
|
||||
define <16 x i8> @testVINSBVLX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
|
||||
; CHECK-LABEL: testVINSBVLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsbvlx v2, r5, v3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i64 %b, <16 x i8> %c)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i64, <16 x i8>)
|
||||
|
||||
define <16 x i8> @testVINSBVRX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
|
||||
; CHECK-LABEL: testVINSBVRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinsbvrx v2, r5, v3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i64 %b, <16 x i8> %c)
|
||||
ret <16 x i8> %0
|
||||
}
|
||||
declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i64, <16 x i8>)
|
||||
|
||||
define <8 x i16> @testVINSHVLX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
|
||||
; CHECK-LABEL: testVINSHVLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinshvlx v2, r5, v3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i64 %b, <8 x i16> %c)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i64, <8 x i16>)
|
||||
|
||||
define <8 x i16> @testVINSHVRX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
|
||||
entry:
|
||||
%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i64 %b, <8 x i16> %c)
|
||||
ret <8 x i16> %0
|
||||
}
|
||||
declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i64, <8 x i16>)
|
||||
|
||||
define <4 x i32> @testVINSWVLX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: testVINSWVLX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinswvlx v2, r5, v3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i64 %b, <4 x i32> %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i64, <4 x i32>)
|
||||
|
||||
define <4 x i32> @testVINSWVRX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: testVINSWVRX:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vinswvrx v2, r5, v3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
|
||||
|
|
|
|||
Loading…
Reference in New Issue