forked from OSchip/llvm-project
[AMDGPU] Allow spilling FP to memory
If there are no available lanes in a reserved VGPR, no free SGPR, and no unused CSR VGPR when trying to save the FP it needs to be spilled to memory as a last resort. This can be done in the prolog/epilog if we manually add the spill and manage exec. Differential Revision: https://reviews.llvm.org/D79610
This commit is contained in:
Austin Kerbow
parent
e1ed4d9eb5
commit
09253b608a
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@ -593,6 +593,47 @@ bool SIFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
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llvm_unreachable("Invalid TargetStackID::Value");
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}
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// Activate all lanes, returns saved exec.
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static Register buildScratchExecCopy(LivePhysRegs &LiveRegs,
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MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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bool IsProlog) {
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Register ScratchExecCopy;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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DebugLoc DL;
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if (LiveRegs.empty()) {
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if (IsProlog) {
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LiveRegs.init(TRI);
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LiveRegs.addLiveIns(MBB);
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if (FuncInfo->SGPRForFPSaveRestoreCopy)
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LiveRegs.removeReg(FuncInfo->SGPRForFPSaveRestoreCopy);
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} else {
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// In epilog.
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LiveRegs.init(*ST.getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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LiveRegs.stepBackward(*MBBI);
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}
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}
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ScratchExecCopy = findScratchNonCalleeSaveRegister(
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MRI, LiveRegs, *TRI.getWaveMaskRegClass());
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if (!IsProlog)
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LiveRegs.removeReg(ScratchExecCopy);
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const unsigned OrSaveExec =
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ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
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BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy).addImm(-1);
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return ScratchExecCopy;
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}
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void SIFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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@ -621,6 +662,15 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
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// turn on all lanes before doing the spill to memory.
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Register ScratchExecCopy;
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bool HasFPSaveIndex = FuncInfo->FramePointerSaveIndex.hasValue();
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bool SpillFPToMemory = false;
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// A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
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// Otherwise we are spilling the FP to memory.
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if (HasFPSaveIndex) {
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SpillFPToMemory = MFI.getStackID(*FuncInfo->FramePointerSaveIndex) !=
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TargetStackID::SGPRSpill;
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}
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// Emit the copy if we need an FP, and are using a free SGPR to save it.
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if (FuncInfo->SGPRForFPSaveRestoreCopy) {
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
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@ -636,25 +686,8 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
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if (!Reg.FI.hasValue())
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continue;
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if (!ScratchExecCopy) {
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if (LiveRegs.empty()) {
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LiveRegs.init(TRI);
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LiveRegs.addLiveIns(MBB);
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if (FuncInfo->SGPRForFPSaveRestoreCopy)
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LiveRegs.removeReg(FuncInfo->SGPRForFPSaveRestoreCopy);
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}
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ScratchExecCopy
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= findScratchNonCalleeSaveRegister(MRI, LiveRegs,
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*TRI.getWaveMaskRegClass());
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assert(FuncInfo->SGPRForFPSaveRestoreCopy != ScratchExecCopy);
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const unsigned OrSaveExec = ST.isWave32() ?
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AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
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BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec),
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ScratchExecCopy)
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.addImm(-1);
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}
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if (!ScratchExecCopy)
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ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
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buildPrologSpill(LiveRegs, MBB, MBBI, TII, Reg.VGPR,
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FuncInfo->getScratchRSrcReg(),
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@ -662,30 +695,50 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
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Reg.FI.getValue());
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}
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if (HasFPSaveIndex && SpillFPToMemory) {
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const int FI = FuncInfo->FramePointerSaveIndex.getValue();
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assert(!MFI.isDeadObjectIndex(FI));
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if (!ScratchExecCopy)
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ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
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MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister(
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MRI, LiveRegs, AMDGPU::VGPR_32RegClass);
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
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.addReg(FramePtrReg);
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buildPrologSpill(LiveRegs, MBB, MBBI, TII, TmpVGPR,
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FuncInfo->getScratchRSrcReg(), StackPtrReg,
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FuncInfo->FramePointerSaveIndex.getValue());
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}
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if (ScratchExecCopy) {
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// FIXME: Split block and make terminator.
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unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
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MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
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BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
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.addReg(ScratchExecCopy, RegState::Kill);
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.addReg(ScratchExecCopy, RegState::Kill);
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LiveRegs.addReg(ScratchExecCopy);
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}
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if (FuncInfo->FramePointerSaveIndex) {
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// In this case, spill the FP to a reserved VGPR.
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if (HasFPSaveIndex && !SpillFPToMemory) {
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const int FI = FuncInfo->FramePointerSaveIndex.getValue();
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assert(!MFI.isDeadObjectIndex(FI) &&
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MFI.getStackID(FI) == TargetStackID::SGPRSpill);
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ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill
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= FuncInfo->getSGPRToVGPRSpills(FI);
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assert(!MFI.isDeadObjectIndex(FI));
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assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
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ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
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FuncInfo->getSGPRToVGPRSpills(FI);
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assert(Spill.size() == 1);
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// Save FP before setting it up.
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// FIXME: This should respect spillSGPRToVGPR;
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BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
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Spill[0].VGPR)
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.addReg(FramePtrReg)
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.addImm(Spill[0].Lane)
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.addReg(Spill[0].VGPR, RegState::Undef);
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.addReg(FramePtrReg)
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.addImm(Spill[0].Lane)
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.addReg(Spill[0].VGPR, RegState::Undef);
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}
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if (TRI.needsStackRealignment(MF)) {
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@ -706,13 +759,13 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
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// s_add_u32 tmp_reg, s32, NumBytes
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// s_and_b32 s32, tmp_reg, 0b111...0000
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)
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.addReg(StackPtrReg)
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.addImm((Alignment - 1) * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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.addReg(StackPtrReg)
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.addImm((Alignment - 1) * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
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.addReg(ScratchSPReg, RegState::Kill)
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.addImm(-Alignment * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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.addReg(ScratchSPReg, RegState::Kill)
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.addImm(-Alignment * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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FuncInfo->setIsStackRealigned(true);
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} else if ((HasFP = hasFP(MF))) {
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// If we need a base pointer, set it up here. It's whatever the value of
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@ -720,15 +773,15 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
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// allocated after this, so we can still use the base pointer to reference
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// locals.
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
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.addReg(StackPtrReg)
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.setMIFlag(MachineInstr::FrameSetup);
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.addReg(StackPtrReg)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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if (HasFP && RoundedSize != 0) {
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)
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.addReg(StackPtrReg)
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.addImm(RoundedSize * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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.addReg(StackPtrReg)
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.addImm(RoundedSize * ST.getWavefrontSize())
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.setMIFlag(MachineInstr::FrameSetup);
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}
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assert((!HasFP || (FuncInfo->SGPRForFPSaveRestoreCopy ||
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@ -758,9 +811,17 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
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uint32_t RoundedSize = FuncInfo->isStackRealigned()
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? NumBytes + MFI.getMaxAlign().value()
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: NumBytes;
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const Register StackPtrReg = FuncInfo->getStackPtrOffsetReg();
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const Register FramePtrReg = FuncInfo->getFrameOffsetReg();
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bool HasFPSaveIndex = FuncInfo->FramePointerSaveIndex.hasValue();
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bool SpillFPToMemory = false;
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if (HasFPSaveIndex) {
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SpillFPToMemory = MFI.getStackID(*FuncInfo->FramePointerSaveIndex) !=
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TargetStackID::SGPRSpill;
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}
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if (RoundedSize != 0 && hasFP(MF)) {
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const Register StackPtrReg = FuncInfo->getStackPtrOffsetReg();
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
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.addReg(StackPtrReg)
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.addImm(RoundedSize * ST.getWavefrontSize())
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@ -768,55 +829,49 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
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}
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if (FuncInfo->SGPRForFPSaveRestoreCopy) {
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->getFrameOffsetReg())
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.addReg(FuncInfo->SGPRForFPSaveRestoreCopy)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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if (FuncInfo->FramePointerSaveIndex) {
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const int FI = FuncInfo->FramePointerSaveIndex.getValue();
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assert(!MF.getFrameInfo().isDeadObjectIndex(FI) &&
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MF.getFrameInfo().getStackID(FI) == TargetStackID::SGPRSpill);
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ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill
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= FuncInfo->getSGPRToVGPRSpills(FI);
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assert(Spill.size() == 1);
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BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
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FuncInfo->getFrameOffsetReg())
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.addReg(Spill[0].VGPR)
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.addImm(Spill[0].Lane);
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
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.addReg(FuncInfo->SGPRForFPSaveRestoreCopy)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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Register ScratchExecCopy;
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for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg
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: FuncInfo->getSGPRSpillVGPRs()) {
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if (HasFPSaveIndex) {
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const int FI = FuncInfo->FramePointerSaveIndex.getValue();
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assert(!MFI.isDeadObjectIndex(FI));
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if (SpillFPToMemory) {
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if (!ScratchExecCopy)
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ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false);
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MCPhysReg TempVGPR = findScratchNonCalleeSaveRegister(
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MRI, LiveRegs, AMDGPU::VGPR_32RegClass);
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buildEpilogReload(LiveRegs, MBB, MBBI, TII, TempVGPR,
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FuncInfo->getScratchRSrcReg(), StackPtrReg, FI);
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BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), FramePtrReg)
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.addReg(TempVGPR, RegState::Kill);
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} else {
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// Reload from VGPR spill.
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assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
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ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
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FuncInfo->getSGPRToVGPRSpills(FI);
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assert(Spill.size() == 1);
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BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
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FramePtrReg)
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.addReg(Spill[0].VGPR)
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.addImm(Spill[0].Lane);
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}
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}
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for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg :
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FuncInfo->getSGPRSpillVGPRs()) {
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if (!Reg.FI.hasValue())
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continue;
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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if (!ScratchExecCopy) {
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// See emitPrologue
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if (LiveRegs.empty()) {
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LiveRegs.init(*ST.getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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LiveRegs.stepBackward(*MBBI);
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}
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ScratchExecCopy = findScratchNonCalleeSaveRegister(
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MRI, LiveRegs, *TRI.getWaveMaskRegClass());
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LiveRegs.removeReg(ScratchExecCopy);
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const unsigned OrSaveExec =
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ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
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BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy)
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.addImm(-1);
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}
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if (!ScratchExecCopy)
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ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false);
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buildEpilogReload(LiveRegs, MBB, MBBI, TII, Reg.VGPR,
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FuncInfo->getScratchRSrcReg(),
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FuncInfo->getStackPtrOffsetReg(), Reg.FI.getValue());
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FuncInfo->getScratchRSrcReg(), StackPtrReg,
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Reg.FI.getValue());
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}
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if (ScratchExecCopy) {
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@ -824,7 +879,7 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
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unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
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MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
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BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
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.addReg(ScratchExecCopy, RegState::Kill);
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.addReg(ScratchExecCopy, RegState::Kill);
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}
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}
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@ -906,7 +961,7 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
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if (MFI->isEntryFunction())
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return;
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const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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@ -934,12 +989,14 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
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if (!HasFP)
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return;
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// We need to save and restore the current FP.
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// 1: If there is already a VGPR with free lanes, use it. We
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// may already have to pay the penalty for spilling a CSR VGPR.
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if (MFI->haveFreeLanesForSGPRSpill(MF, 1)) {
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int NewFI = MF.getFrameInfo().CreateStackObject(4, 4, true, nullptr,
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TargetStackID::SGPRSpill);
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// If there is already a VGPR with free lanes, use it. We may already have
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// to pay the penalty for spilling a CSR VGPR.
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if (!MFI->allocateSGPRSpillToVGPR(MF, NewFI))
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llvm_unreachable("allocate SGPR spill should have worked");
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@ -952,16 +1009,22 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
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return;
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}
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// 2: Next, try to save the FP in an unused SGPR.
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MFI->SGPRForFPSaveRestoreCopy = findUnusedSGPRNonCalleeSaved(MF.getRegInfo());
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if (!MFI->SGPRForFPSaveRestoreCopy) {
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// There's no free lane to spill, and no free register to save FP, so we're
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// forced to spill another VGPR to use for the spill.
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int NewFI = MF.getFrameInfo().CreateStackObject(4, 4, true, nullptr,
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TargetStackID::SGPRSpill);
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if (!MFI->allocateSGPRSpillToVGPR(MF, NewFI))
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llvm_unreachable("allocate SGPR spill should have worked");
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MFI->FramePointerSaveIndex = NewFI;
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if (MFI->allocateSGPRSpillToVGPR(MF, NewFI)) {
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// 3: There's no free lane to spill, and no free register to save FP, so
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// we're forced to spill another VGPR to use for the spill.
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MFI->FramePointerSaveIndex = NewFI;
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} else {
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// 4: If all else fails, spill the FP to memory.
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MFI->FramePointerSaveIndex =
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FrameInfo.CreateSpillStackObject(4, Align(4));
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}
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LLVM_DEBUG(
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auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
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@ -459,6 +459,115 @@ define void @ipra_call_with_stack() #0 {
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ret void
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}
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; With no free registers, we must spill the FP to memory.
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; GCN-LABEL: {{^}}callee_need_to_spill_fp_to_memory:
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; GCN: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
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; GCN: v_mov_b32_e32 [[TMP_VGPR1:v[0-9]+]], s33
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; GCN: buffer_store_dword [[TMP_VGPR1]], off, s[0:3], s32 offset:[[OFF:[0-9]+]]
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; GCN: s_mov_b64 exec, [[COPY_EXEC1]]
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; GCN: s_mov_b32 s33, s32
|
||||
; GCN: s_or_saveexec_b64 [[COPY_EXEC2:s\[[0-9]+:[0-9]+\]]], -1{{$}}
|
||||
; GCN: buffer_load_dword [[TMP_VGPR2:v[0-9]+]], off, s[0:3], s32 offset:[[OFF]]
|
||||
; GCN: s_waitcnt vmcnt(0)
|
||||
; GCN: v_readfirstlane_b32 s33, [[TMP_VGPR2]]
|
||||
; GCN: s_mov_b64 exec, [[COPY_EXEC2]]
|
||||
; GCN: s_setpc_b64
|
||||
define void @callee_need_to_spill_fp_to_memory() #1 {
|
||||
call void asm sideeffect "; clobber nonpreserved SGPRs",
|
||||
"~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
|
||||
,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
|
||||
,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
|
||||
,~{vcc}"()
|
||||
|
||||
call void asm sideeffect "; clobber all VGPRs",
|
||||
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
|
||||
,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
|
||||
,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
|
||||
,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}
|
||||
,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49}
|
||||
,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
|
||||
,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69}
|
||||
,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79}
|
||||
,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89}
|
||||
,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
||||
,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
|
||||
,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
|
||||
,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
|
||||
,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139}
|
||||
,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149}
|
||||
,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159}
|
||||
,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169}
|
||||
,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179}
|
||||
,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189}
|
||||
,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199}
|
||||
,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
|
||||
,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219}
|
||||
,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229}
|
||||
,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239}
|
||||
,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249}
|
||||
,~{v250},~{v251},~{v252},~{v253},~{v254},~{v255}"()
|
||||
ret void
|
||||
}
|
||||
|
||||
; If we have a reserved VGPR that can be used for SGPR spills, we may still
|
||||
; need to spill the FP to memory if there are no free lanes in the reserved
|
||||
; VGPR.
|
||||
; GCN-LABEL: {{^}}callee_need_to_spill_fp_to_memory_full_reserved_vgpr:
|
||||
; GCN: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
|
||||
; GCN: v_mov_b32_e32 [[TMP_VGPR1:v[0-9]+]], s33
|
||||
; GCN: buffer_store_dword [[TMP_VGPR1]], off, s[0:3], s32 offset:[[OFF:[0-9]+]]
|
||||
; GCN: s_mov_b64 exec, [[COPY_EXEC1]]
|
||||
; GCN-NOT: v_writelane_b32 v40, s33
|
||||
; GCN: s_mov_b32 s33, s32
|
||||
; GCN-NOT: v_readlane_b32 s33, v40
|
||||
; GCN: s_or_saveexec_b64 [[COPY_EXEC2:s\[[0-9]+:[0-9]+\]]], -1{{$}}
|
||||
; GCN: buffer_load_dword [[TMP_VGPR2:v[0-9]+]], off, s[0:3], s32 offset:[[OFF]]
|
||||
; GCN: v_readfirstlane_b32 s33, [[TMP_VGPR2]]
|
||||
; GCN: s_mov_b64 exec, [[COPY_EXEC2]]
|
||||
; GCN: s_setpc_b64
|
||||
define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #1 {
|
||||
call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
|
||||
"~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
|
||||
,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
|
||||
,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
|
||||
,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
|
||||
,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59}
|
||||
,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65},~{s66},~{s67},~{s68},~{s69}
|
||||
,~{s70},~{s71},~{s72},~{s73},~{s74},~{s75},~{s76},~{s77},~{s78},~{s79}
|
||||
,~{s80},~{s81},~{s82},~{s83},~{s84},~{s85},~{s86},~{s87},~{s88},~{s89}
|
||||
,~{s90},~{s91},~{s92},~{s93},~{s94},~{s95},~{s96},~{s97},~{s98},~{s99}
|
||||
,~{s100},~{s101},~{s102},~{s39},~{vcc}"()
|
||||
|
||||
call void asm sideeffect "; clobber all VGPRs except CSR v40",
|
||||
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
|
||||
,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
|
||||
,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
|
||||
,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}
|
||||
,~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49}
|
||||
,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
|
||||
,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69}
|
||||
,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79}
|
||||
,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89}
|
||||
,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
||||
,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
|
||||
,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
|
||||
,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
|
||||
,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139}
|
||||
,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149}
|
||||
,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159}
|
||||
,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169}
|
||||
,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179}
|
||||
,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189}
|
||||
,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199}
|
||||
,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
|
||||
,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219}
|
||||
,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229}
|
||||
,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239}
|
||||
,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249}
|
||||
,~{v250},~{v251},~{v252},~{v253},~{v254},~{v255}"()
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind "frame-pointer"="all" }
|
||||
attributes #2 = { nounwind "frame-pointer"="non-leaf" }
|
||||
|
|
|
|||
Loading…
Reference in New Issue