forked from OSchip/llvm-project
[msan] Instrument masked.store, masked.load intrinsics.
Summary: Instrument masked store/load intrinsics. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46785 llvm-svn: 332402
This commit is contained in:
Evgeniy Stepanov
parent
7bfd705492
commit
091fed94ae
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@ -2537,11 +2537,98 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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insertShadowCheck(Shadow, Origin, &I);
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}
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void handleMaskedStore(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *V = I.getArgOperand(0);
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Value *Addr = I.getArgOperand(1);
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unsigned Align = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
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Value *Mask = I.getArgOperand(3);
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Value *Shadow = getShadow(V);
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Value *ShadowPtr;
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Value *OriginPtr;
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std::tie(ShadowPtr, OriginPtr) = getShadowOriginPtr(
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Addr, IRB, Shadow->getType(), Align, /*isStore*/ true);
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if (ClCheckAccessAddress) {
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insertShadowCheck(Addr, &I);
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// Uninitialized mask is kind of like uninitialized address, but not as
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// scary.
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insertShadowCheck(Mask, &I);
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}
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IRB.CreateMaskedStore(Shadow, ShadowPtr, Align, Mask);
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if (MS.TrackOrigins) {
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auto &DL = F.getParent()->getDataLayout();
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paintOrigin(IRB, getOrigin(V), OriginPtr,
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DL.getTypeStoreSize(Shadow->getType()),
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std::max(Align, kMinOriginAlignment));
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}
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}
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bool handleMaskedLoad(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *Addr = I.getArgOperand(0);
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unsigned Align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
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Value *Mask = I.getArgOperand(2);
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Value *PassThru = I.getArgOperand(3);
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Type *ShadowTy = getShadowTy(&I);
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Value *ShadowPtr, *OriginPtr;
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if (PropagateShadow) {
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std::tie(ShadowPtr, OriginPtr) =
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getShadowOriginPtr(Addr, IRB, ShadowTy, Align, /*isStore*/ false);
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setShadow(&I, IRB.CreateMaskedLoad(ShadowPtr, Align, Mask,
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getShadow(PassThru), "_msmaskedld"));
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} else {
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setShadow(&I, getCleanShadow(&I));
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}
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if (ClCheckAccessAddress) {
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insertShadowCheck(Addr, &I);
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insertShadowCheck(Mask, &I);
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}
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if (MS.TrackOrigins) {
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if (PropagateShadow) {
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// Choose between PassThru's and the loaded value's origins.
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Value *MaskedPassThruShadow = IRB.CreateAnd(
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getShadow(PassThru), IRB.CreateSExt(IRB.CreateNeg(Mask), ShadowTy));
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Value *Acc = IRB.CreateExtractElement(
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MaskedPassThruShadow, ConstantInt::get(IRB.getInt32Ty(), 0));
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for (int i = 1, N = PassThru->getType()->getVectorNumElements(); i < N;
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++i) {
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Value *More = IRB.CreateExtractElement(
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MaskedPassThruShadow, ConstantInt::get(IRB.getInt32Ty(), i));
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Acc = IRB.CreateOr(Acc, More);
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}
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Value *Origin = IRB.CreateSelect(
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IRB.CreateICmpNE(Acc, Constant::getNullValue(Acc->getType())),
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getOrigin(PassThru), IRB.CreateLoad(OriginPtr));
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setOrigin(&I, Origin);
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} else {
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setOrigin(&I, getCleanOrigin());
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}
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}
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return true;
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}
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void visitIntrinsicInst(IntrinsicInst &I) {
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switch (I.getIntrinsicID()) {
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case Intrinsic::bswap:
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handleBswap(I);
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break;
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case Intrinsic::masked_store:
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handleMaskedStore(I);
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break;
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case Intrinsic::masked_load:
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handleMaskedLoad(I);
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break;
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case Intrinsic::x86_sse_stmxcsr:
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handleStmxcsr(I);
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break;
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@ -0,0 +1,124 @@
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,CHECK-ORIGIN
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; RUN: opt < %s -msan -msan-check-access-address=1 -S | FileCheck %s --check-prefix=ADDR
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
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declare <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
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define void @Store(<4 x i64>* %p, <4 x i64> %v, <4 x i1> %mask) sanitize_memory {
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entry:
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tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
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ret void
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}
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; CHECK-LABEL: @Store(
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; CHECK: %[[A:.*]] = load <4 x i64>, {{.*}}@__msan_param_tls to i64), i64 8)
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; CHECK-ORIGIN: %[[O:.*]] = load i32, {{.*}}@__msan_param_origin_tls to i64), i64 8)
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; CHECK: %[[B:.*]] = ptrtoint <4 x i64>* %p to i64
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; CHECK: %[[C:.*]] = xor i64 %[[B]], 87960930222080
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; CHECK: %[[D:.*]] = inttoptr i64 %[[C]] to <4 x i64>*
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; CHECK-ORIGIN: %[[E:.*]] = add i64 %[[C]], 17592186044416
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; CHECK-ORIGIN: %[[F:.*]] = and i64 %[[E]], -4
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; CHECK-ORIGIN: %[[G:.*]] = inttoptr i64 %[[F]] to i32*
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; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %[[A]], <4 x i64>* %[[D]], i32 1, <4 x i1> %mask)
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; CHECK-ORIGIN: store i32 %[[O]], i32* %[[G]], align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 1
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 2
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 3
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 4
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 5
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 6
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK-ORIGIN: getelementptr i32, i32* %[[G]], i32 7
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; CHECK-ORIGIN: store i32 %[[O]], i32* {{.*}}, align 4
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; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
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; CHECK: ret void
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; ADDR-LABEL: @Store(
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; ADDR: %[[MASKSHADOW:.*]] = load <4 x i1>, {{.*}}@__msan_param_tls to i64), i64 40)
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; ADDR: %[[ADDRSHADOW:.*]] = load i64, {{.*}}[100 x i64]* @__msan_param_tls, i32 0, i32 0)
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; ADDR: %[[ADDRBAD:.*]] = icmp ne i64 %[[ADDRSHADOW]], 0
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; ADDR: br i1 %[[ADDRBAD]], label {{.*}}, label {{.*}}
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; ADDR: call void @__msan_warning_noreturn()
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; ADDR: %[[MASKSHADOWFLAT:.*]] = bitcast <4 x i1> %[[MASKSHADOW]] to i4
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; ADDR: %[[MASKBAD:.*]] = icmp ne i4 %[[MASKSHADOWFLAT]], 0
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; ADDR: br i1 %[[MASKBAD]], label {{.*}}, label {{.*}}
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; ADDR: call void @__msan_warning_noreturn()
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; ADDR: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
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; ADDR: ret void
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define <4 x double> @Load(<4 x double>* %p, <4 x double> %v, <4 x i1> %mask) sanitize_memory {
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entry:
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%x = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v)
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ret <4 x double> %x
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}
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; CHECK-LABEL: @Load(
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; CHECK: %[[A:.*]] = load <4 x i64>, {{.*}}@__msan_param_tls to i64), i64 8)
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; CHECK-ORIGIN: %[[O:.*]] = load i32, {{.*}}@__msan_param_origin_tls to i64), i64 8)
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; CHECK: %[[B:.*]] = ptrtoint <4 x double>* %p to i64
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; CHECK: %[[C:.*]] = xor i64 %[[B]], 87960930222080
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; CHECK: %[[D:.*]] = inttoptr i64 %[[C]] to <4 x i64>*
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; CHECK-ORIGIN: %[[E:.*]] = add i64 %[[C]], 17592186044416
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; CHECK-ORIGIN: %[[F:.*]] = and i64 %[[E]], -4
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; CHECK-ORIGIN: %[[G:.*]] = inttoptr i64 %[[F]] to i32*
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; CHECK: %[[E:.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %[[D]], i32 1, <4 x i1> %mask, <4 x i64> %[[A]])
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; CHECK-ORIGIN: %[[H:.*]] = load i32, i32* %[[G]]
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; CHECK-ORIGIN: %[[O2:.*]] = select i1 %{{.*}}, i32 %[[O]], i32 %[[H]]
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; CHECK: %[[X:.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v)
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; CHECK: store <4 x i64> %[[E]], {{.*}}@__msan_retval_tls
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; CHECK-ORIGIN: store i32 %[[O2]], i32* @__msan_retval_origin_tls
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; CHECK: ret <4 x double> %[[X]]
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; ADDR-LABEL: @Load(
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; ADDR: %[[MASKSHADOW:.*]] = load <4 x i1>, {{.*}}@__msan_param_tls to i64), i64 40)
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; ADDR: %[[ADDRSHADOW:.*]] = load i64, {{.*}}[100 x i64]* @__msan_param_tls, i32 0, i32 0)
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; ADDR: %[[ADDRBAD:.*]] = icmp ne i64 %[[ADDRSHADOW]], 0
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; ADDR: br i1 %[[ADDRBAD]], label {{.*}}, label {{.*}}
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; ADDR: call void @__msan_warning_noreturn()
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; ADDR: %[[MASKSHADOWFLAT:.*]] = bitcast <4 x i1> %[[MASKSHADOW]] to i4
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; ADDR: %[[MASKBAD:.*]] = icmp ne i4 %[[MASKSHADOWFLAT]], 0
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; ADDR: br i1 %[[MASKBAD]], label {{.*}}, label {{.*}}
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; ADDR: call void @__msan_warning_noreturn()
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; ADDR: = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v)
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; ADDR: ret <4 x double>
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define void @StoreNoSanitize(<4 x i64>* %p, <4 x i64> %v, <4 x i1> %mask) {
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entry:
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tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
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ret void
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}
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; CHECK-LABEL: @StoreNoSanitize(
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; CHECK: %[[B:.*]] = ptrtoint <4 x i64>* %p to i64
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; CHECK: %[[C:.*]] = xor i64 %[[B]], 87960930222080
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; CHECK: %[[D:.*]] = inttoptr i64 %[[C]] to <4 x i64>*
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; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* %[[D]], i32 1, <4 x i1> %mask)
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; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
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; CHECK: ret void
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define <4 x double> @LoadNoSanitize(<4 x double>* %p, <4 x double> %v, <4 x i1> %mask) {
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entry:
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%x = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v)
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ret <4 x double> %x
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}
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; CHECK-LABEL: @LoadNoSanitize(
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; CHECK: %[[X:.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v)
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; CHECK: store <4 x i64> zeroinitializer, {{.*}}@__msan_retval_tls to <4 x i64>*)
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; CHECK: ret <4 x double> %[[X]]
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