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[X86] Add 512-bit shuffle test cases for concatenating 128/256-bits with zeros in the upper portion. 

We should recognize this and just use a mov that will zero the upper bits.

llvm-svn: 324708
This commit is contained in:
Craig Topper 2018-02-09 05:54:31 +00:00
parent 7ac1c78062
commit 090e41d0cc
1 changed files with 34 additions and 0 deletions
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34
llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
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@ -2761,3 +2761,37 @@ define <2 x i64> @test_v8i64_2_5 (<8 x i64> %v) {
%res = shufflevector <8 x i64> %v, <8 x i64> undef, <2 x i32> <i32 2, i32 5>
ret <2 x i64> %res
}
define <8 x i64> @test_v8i64_insert_zero_128(<8 x i64> %a) {
; AVX512F-LABEL: test_v8i64_insert_zero_128:
; AVX512F: # %bb.0:
; AVX512F-NEXT: movb $3, %al
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: retq
;
; AVX512F-32-LABEL: test_v8i64_insert_zero_128:
; AVX512F-32: # %bb.0:
; AVX512F-32-NEXT: movb $3, %al
; AVX512F-32-NEXT: kmovw %eax, %k1
; AVX512F-32-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z}
; AVX512F-32-NEXT: retl
%res = shufflevector <8 x i64> %a, <8 x i64> <i64 0, i64 0, i64 0, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9>
ret <8 x i64> %res
}
define <8 x i64> @test_v8i64_insert_zero_256(<8 x i64> %a) {
; AVX512F-LABEL: test_v8i64_insert_zero_256:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512F-32-LABEL: test_v8i64_insert_zero_256:
; AVX512F-32: # %bb.0:
; AVX512F-32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[0,1,0,1]
; AVX512F-32-NEXT: retl
%res = shufflevector <8 x i64> %a, <8 x i64> <i64 0, i64 0, i64 0, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 8, i32 9>
ret <8 x i64> %res
}