forked from OSchip/llvm-project
[InstCombine] move/add tests for trunc-of-lshr; NFC
Planning to reframe a proposed transform in terms of demanded bits as suggested in D110170. The new tests end with an 'or'.
This commit is contained in:
Sanjay Patel
parent
11c533e1ea
commit
08ef71ca92
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@ -2,9 +2,6 @@
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; RUN: opt < %s -instcombine -data-layout="n8:16:32" -S | FileCheck %s
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; RUN: opt < %s -instcombine -data-layout="n16" -S | FileCheck %s
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declare void @use6(i6)
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declare void @use8(i8)
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; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=35792
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define i16 @zext_add(i8 %x) {
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@ -212,111 +209,3 @@ define <2 x i16> @zext_shl_vec_undef(<2 x i8> %x) {
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%r = and <2 x i16> %b, %z
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ret <2 x i16> %r
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}
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define i6 @trunc_lshr(i8 %x) {
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; CHECK-LABEL: @trunc_lshr(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 14
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 14
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ret i6 %r
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}
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define i6 @trunc_lshr_exact_mask(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_exact_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 15
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ret i6 %r
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}
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define i6 @trunc_lshr_big_mask(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_big_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 31
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 31
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ret i6 %r
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}
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define i6 @trunc_lshr_use1(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_use1(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: call void @use8(i8 [[S]])
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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call void @use8(i8 %s)
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%t = trunc i8 %s to i6
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%r = and i6 %t, 15
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ret i6 %r
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}
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define i6 @trunc_lshr_use2(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_use2(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: call void @use6(i6 [[T]])
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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call void @use6(i6 %t)
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%r = and i6 %t, 15
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ret i6 %r
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}
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define <2 x i7> @trunc_lshr_vec_splat(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_vec_splat(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 5, i16 5>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 5, i16 5>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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define <2 x i7> @trunc_lshr_vec_splat_exact_mask(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_vec_splat_exact_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 6, i16 6>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 6, i16 6>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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define <2 x i7> @trunc_lshr_big_shift(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_big_shift(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 7, i16 7>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 7, i16 7>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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@ -0,0 +1,152 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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declare void @use6(i6)
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declare void @use8(i8)
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define i6 @trunc_lshr(i8 %x) {
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; CHECK-LABEL: @trunc_lshr(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 14
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 14
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ret i6 %r
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}
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define i6 @trunc_lshr_exact_mask(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_exact_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 15
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ret i6 %r
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}
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define i6 @trunc_lshr_big_mask(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_big_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 31
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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%r = and i6 %t, 31
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ret i6 %r
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}
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define i6 @trunc_lshr_use1(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_use1(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: call void @use8(i8 [[S]])
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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call void @use8(i8 %s)
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%t = trunc i8 %s to i6
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%r = and i6 %t, 15
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ret i6 %r
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}
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define i6 @trunc_lshr_use2(i8 %x) {
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; CHECK-LABEL: @trunc_lshr_use2(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: call void @use6(i6 [[T]])
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; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 2
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%t = trunc i8 %s to i6
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call void @use6(i6 %t)
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%r = and i6 %t, 15
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ret i6 %r
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}
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define <2 x i7> @trunc_lshr_vec_splat(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_vec_splat(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 5, i16 5>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 5, i16 5>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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define <2 x i7> @trunc_lshr_vec_splat_exact_mask(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_vec_splat_exact_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 6, i16 6>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 6, i16 6>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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define <2 x i7> @trunc_lshr_big_shift(<2 x i16> %x) {
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; CHECK-LABEL: @trunc_lshr_big_shift(
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 7, i16 7>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
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; CHECK-NEXT: ret <2 x i7> [[R]]
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;
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%s = lshr <2 x i16> %x, <i16 7, i16 7>
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%t = trunc <2 x i16> %s to <2 x i7>
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%r = and <2 x i7> %t, <i7 1, i7 1>
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ret <2 x i7> %r
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}
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define i6 @or_trunc_lshr(i8 %x) {
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; CHECK-LABEL: @or_trunc_lshr(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 1
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = or i6 [[T]], -32
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 1
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%t = trunc i8 %s to i6
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%r = or i6 %t, 32 ; 0b100000
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ret i6 %r
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}
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define i6 @or_trunc_lshr_more(i8 %x) {
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; CHECK-LABEL: @or_trunc_lshr_more(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = or i6 [[T]], -4
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 4
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%t = trunc i8 %s to i6
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%r = or i6 %t, 60 ; 0b111100
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ret i6 %r
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}
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define i6 @or_trunc_lshr_small_mask(i8 %x) {
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; CHECK-LABEL: @or_trunc_lshr_small_mask(
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; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6
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; CHECK-NEXT: [[R:%.*]] = or i6 [[T]], -8
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; CHECK-NEXT: ret i6 [[R]]
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;
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%s = lshr i8 %x, 4
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%t = trunc i8 %s to i6
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%r = or i6 %t, 56 ; 0b111000
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ret i6 %r
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}
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