forked from OSchip/llvm-project
Add a deterministic finite automaton based packetizer for VLIW architectures
llvm-svn: 145629
This commit is contained in:
Anshuman Dasgupta
parent
e0a64f7302
commit
08ebdc1e71
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@ -1858,6 +1858,9 @@ $(ObjDir)/ARMGenDecoderTables.inc.tmp : ARM.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) decoder tables with tblgen"
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$(Verb) $(LLVMTableGen) -gen-arm-decoder -o $(call SYSPATH, $@) $<
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$(ObjDir)/%GenDFAPacketizer.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) DFA packetizer tables with tblgen"
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$(Verb) $(LLVMTableGen) -gen-dfa-packetizer -o $(call SYSPATH, $@) $<
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clean-local::
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-$(Verb) $(RM) -f $(INCFiles)
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@ -0,0 +1,78 @@
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//=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DFAPACKETIZER_H
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#define LLVM_CODEGEN_DFAPACKETIZER_H
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#include "llvm/ADT/DenseMap.h"
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namespace llvm {
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class MCInstrDesc;
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class MachineInstr;
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class InstrItineraryData;
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class DFAPacketizer {
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private:
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typedef std::pair<unsigned, unsigned> UnsignPair;
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const InstrItineraryData *InstrItins;
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int CurrentState;
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const int (*DFAStateInputTable)[2];
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const unsigned *DFAStateEntryTable;
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// CachedTable is a map from <FromState, Input> to ToState
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DenseMap<UnsignPair, unsigned> CachedTable;
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// ReadTable - Read the DFA transition table and update CachedTable
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void ReadTable(unsigned int state);
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public:
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DFAPacketizer(const InstrItineraryData* I, const int (*SIT)[2],
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const unsigned* SET);
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// Reset the current state to make all resources available
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void clearResources() {
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CurrentState = 0;
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state
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bool canReserveResources(const llvm::MCInstrDesc* MID);
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change
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void reserveResources(const llvm::MCInstrDesc* MID);
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state
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bool canReserveResources(llvm::MachineInstr* MI);
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change
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void reserveResources(llvm::MachineInstr* MI);
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};
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}
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#endif
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@ -0,0 +1,98 @@
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//=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCInstrItineraries.h"
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using namespace llvm;
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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const unsigned* SET):
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InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
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DFAStateEntryTable(SET) {}
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//
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// ReadTable - Read the DFA transition table and update CachedTable
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//
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// Format of the transition tables:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
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// for the ith state
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//
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void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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// Early exit in case CachedTable has already contains this
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// state's transitions
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if (CachedTable.count(UnsignPair(state,
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DFAStateInputTable[ThisState][0])))
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return;
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for (unsigned i = ThisState; i < NextStateInTable; i++)
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CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
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DFAStateInputTable[i][1];
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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return (CachedTable.count(StateTrans) != 0);
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}
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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}
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state
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bool DFAPacketizer::canReserveResources(llvm::MachineInstr* MI) {
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const llvm::MCInstrDesc& MID = MI->getDesc();
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return canReserveResources(&MID);
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}
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change
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void DFAPacketizer::reserveResources(llvm::MachineInstr* MI) {
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const llvm::MCInstrDesc& MID = MI->getDesc();
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reserveResources(&MID);
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}
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@ -0,0 +1,512 @@
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//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class parses the Schedule.td file and produces an API that can be used
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// to reason about whether an instruction can be added to a packet on a VLIW
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// architecture. The class internally generates a deterministic finite
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// automaton (DFA) that models all possible mappings of machine instructions
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// to functional units as instructions are added to a packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/TableGen/Record.h"
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#include "CodeGenTarget.h"
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#include "DFAPacketizerEmitter.h"
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#include <list>
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using namespace llvm;
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//
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//
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// State represents the usage of machine resources if the packet contains
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// a set of instruction classes.
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//
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// Specifically, currentState is a set of bit-masks
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// The nth bit in a bit-mask indicates whether the nth resource is being used
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// by this state. The set of bit-masks in a state represent the different
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// possible outcomes of transitioning to this state.
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// For example: Consider a two resource architecture: Resource L and Resource M
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// with three instruction classes: L, M, and L_or_M
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// From the initial state (currentState = 0x00), if we add instruction class
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// L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
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// represents the possible resource states that can result from adding a L_or_M
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// instruction
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//
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// Another way of thinking about this transition is we are mapping a NDFA with
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// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10]
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//
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//
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namespace {
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class State {
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public:
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static int currentStateNum;
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int stateNum;
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bool isInitial;
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std::set<unsigned> stateInfo;
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State();
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State(const State& S);
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions
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//
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bool canAddInsnClass(unsigned InsnClass, std::set<unsigned>& PossibleStates);
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};
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} // End anonymous namespace
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namespace {
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struct Transition {
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public:
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static int currentTransitionNum;
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int transitionNum;
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State* from;
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unsigned input;
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State* to;
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Transition(State* from_, unsigned input_, State* to_);
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};
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} // End anonymous namespace
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//
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// Comparators to keep set of states sorted
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//
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namespace {
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struct ltState {
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bool operator()(const State* s1, const State* s2) const;
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};
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} // End anonymous namespace
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//
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// class DFA: deterministic finite automaton for processor resource tracking
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//
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namespace {
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class DFA {
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public:
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DFA();
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// Set of states. Need to keep this sorted to emit the transition table
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std::set<State*, ltState> states;
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// Map from a state to the list of transitions with that state as source
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std::map<State*, SmallVector<Transition*, 16>, ltState> stateTransitions;
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State* currentState;
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// Highest valued Input seen
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unsigned LargestInput;
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//
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// Modify the DFA
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//
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void initialize();
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void addState(State*);
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void addTransition(Transition*);
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//
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// getTransition - Return the state when a transition is made from
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// State From with Input I. If a transition is not found, return NULL
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//
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State* getTransition(State*, unsigned);
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//
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// isValidTransition: Predicate that checks if there is a valid transition
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// from state From on input InsnClass
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//
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bool isValidTransition(State* From, unsigned InsnClass);
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//
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// writeTable: Print out a table representing the DFA
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//
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void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName);
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};
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} // End anonymous namespace
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//
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// Constructors for State, Transition, and DFA
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//
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State::State() :
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stateNum(currentStateNum++), isInitial(false) {}
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State::State(const State& S) :
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stateNum(currentStateNum++), isInitial(S.isInitial),
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stateInfo(S.stateInfo) {}
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Transition::Transition(State* from_, unsigned input_, State* to_) :
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transitionNum(currentTransitionNum++), from(from_), input(input_),
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to(to_) {}
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DFA::DFA() :
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LargestInput(0) {}
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bool ltState::operator()(const State* s1, const State* s2) const {
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return (s1->stateNum < s2->stateNum);
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}
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions
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//
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bool State::canAddInsnClass(unsigned InsnClass,
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std::set<unsigned>& PossibleStates) {
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//
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// Iterate over all resource states in currentState
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//
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bool AddedState = false;
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI) {
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unsigned thisState = *SI;
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//
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// Iterate over all possible resources used in InsnClass
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// For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}
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//
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DenseSet<unsigned> VisitedResourceStates;
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for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
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if ((0x1 << j) & InsnClass) {
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//
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// For each possible resource used in InsnClass, generate the
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// resource state if that resource was used
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//
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unsigned ResultingResourceState = thisState | (0x1 << j);
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//
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// Check if the resulting resource state can be accommodated in this
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// packet
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// We compute ResultingResourceState OR thisState
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// If the result of the OR is different than thisState, it implies
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// that there is at least one resource that can be used to schedule
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// InsnClass in the current packet
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// Insert ResultingResourceState into PossibleStates only if we haven't
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// processed ResultingResourceState before
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//
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if ((ResultingResourceState != thisState) &&
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(VisitedResourceStates.count(ResultingResourceState) == 0)) {
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VisitedResourceStates.insert(ResultingResourceState);
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PossibleStates.insert(ResultingResourceState);
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AddedState = true;
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}
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}
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}
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}
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return AddedState;
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}
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void DFA::initialize() {
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currentState->isInitial = true;
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}
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void DFA::addState(State* S) {
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assert(!states.count(S) && "State already exists");
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states.insert(S);
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}
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void DFA::addTransition(Transition* T) {
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// Update LargestInput
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if (T->input > LargestInput)
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LargestInput = T->input;
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// Add the new transition
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stateTransitions[T->from].push_back(T);
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}
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//
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// getTransition - Return the state when a transition is made from
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// State From with Input I. If a transition is not found, return NULL
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//
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State* DFA::getTransition(State* From, unsigned I) {
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// Do we have a transition from state From?
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if (!stateTransitions.count(From))
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return NULL;
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// Do we have a transition from state From with Input I?
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for (SmallVector<Transition*, 16>::iterator VI =
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stateTransitions[From].begin();
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VI != stateTransitions[From].end(); ++VI)
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if ((*VI)->input == I)
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return (*VI)->to;
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return NULL;
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}
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bool DFA::isValidTransition(State* From, unsigned InsnClass) {
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return (getTransition(From, InsnClass) != NULL);
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}
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int State::currentStateNum = 0;
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int Transition::currentTransitionNum = 0;
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DFAGen::DFAGen(RecordKeeper& R):
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TargetName(CodeGenTarget(R).getName()),
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allInsnClasses(), Records(R) {}
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//
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// writeTableAndAPI - Print out a table representing the DFA and the
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// associated API to create a DFA packetizer
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//
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// Format:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
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// the ith state
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//
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//
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void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
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std::set<State*, ltState>::iterator SI = states.begin();
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// This table provides a map to the beginning of the transitions for State s
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// in DFAStateInputTable i.e.,
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std::vector<int> StateEntry(states.size());
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OS << "namespace llvm {\n\n";
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OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
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// Tracks the total valid transitions encountered so far. It is used
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// to construct the StateEntry table
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int ValidTransitions = 0;
|
||||
for (unsigned i = 0; i < states.size(); ++i, ++SI) {
|
||||
StateEntry[i] = ValidTransitions;
|
||||
for (unsigned j = 0; j <= LargestInput; ++j) {
|
||||
assert (((*SI)->stateNum == (int) i) && "Mismatch in state numbers");
|
||||
if (!isValidTransition(*SI, j))
|
||||
continue;
|
||||
|
||||
OS << "{" << j << ", "
|
||||
<< getTransition(*SI, j)->stateNum
|
||||
<< "}, ";
|
||||
++ValidTransitions;
|
||||
}
|
||||
|
||||
/* If there are no valid transitions from this stage, we need a sentinel
|
||||
transition */
|
||||
if (ValidTransitions == StateEntry[i])
|
||||
OS << "{-1, -1},";
|
||||
|
||||
OS << "\n";
|
||||
}
|
||||
OS << "};\n\n";
|
||||
OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
|
||||
|
||||
// Multiply i by 2 since each entry in DFAStateInputTable is a set of
|
||||
// two numbers
|
||||
for (unsigned i = 0; i < states.size(); ++i)
|
||||
OS << StateEntry[i] << ", ";
|
||||
|
||||
OS << "\n};\n";
|
||||
OS << "} // namespace\n";
|
||||
|
||||
|
||||
//
|
||||
// Emit DFA Packetizer tables if the target is a VLIW machine
|
||||
//
|
||||
std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
|
||||
OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
|
||||
OS << "namespace llvm {\n";
|
||||
OS << "DFAPacketizer* " << SubTargetClassName << "::"
|
||||
<< "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
|
||||
<< " return new DFAPacketizer(IID, " << TargetName
|
||||
<< "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
|
||||
OS << "} // End llvm namespace \n";
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// collectAllInsnClasses - Populate allInsnClasses which is a set of units
|
||||
// used in each stage.
|
||||
//
|
||||
void DFAGen::collectAllInsnClasses(const std::string &Name,
|
||||
Record *ItinData,
|
||||
unsigned &NStages,
|
||||
raw_ostream &OS) {
|
||||
// Collect processor itineraries
|
||||
std::vector<Record*> ProcItinList =
|
||||
Records.getAllDerivedDefinitions("ProcessorItineraries");
|
||||
|
||||
// If just no itinerary then don't bother
|
||||
if (ProcItinList.size() < 2)
|
||||
return;
|
||||
std::map<std::string, unsigned> NameToBitsMap;
|
||||
|
||||
// Parse functional units for all the itineraries.
|
||||
for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
|
||||
Record *Proc = ProcItinList[i];
|
||||
std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
|
||||
|
||||
// Convert macros to bits for each stage
|
||||
for (unsigned i = 0, N = FUs.size(); i < N; ++i)
|
||||
NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
|
||||
}
|
||||
|
||||
const std::vector<Record*> &StageList =
|
||||
ItinData->getValueAsListOfDefs("Stages");
|
||||
|
||||
// The number of stages
|
||||
NStages = StageList.size();
|
||||
|
||||
// For each unit
|
||||
unsigned UnitBitValue = 0;
|
||||
|
||||
// Compute the bitwise or of each unit used in this stage
|
||||
for (unsigned i = 0; i < NStages; ++i) {
|
||||
const Record *Stage = StageList[i];
|
||||
|
||||
// Get unit list
|
||||
const std::vector<Record*> &UnitList =
|
||||
Stage->getValueAsListOfDefs("Units");
|
||||
|
||||
for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
|
||||
// Conduct bitwise or
|
||||
std::string UnitName = UnitList[j]->getName();
|
||||
assert(NameToBitsMap.count(UnitName));
|
||||
UnitBitValue |= NameToBitsMap[UnitName];
|
||||
}
|
||||
|
||||
if (UnitBitValue != 0)
|
||||
allInsnClasses.insert(UnitBitValue);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Run the worklist algorithm to generate the DFA
|
||||
//
|
||||
void DFAGen::run(raw_ostream &OS) {
|
||||
EmitSourceFileHeader("Target DFA Packetizer Tables", OS);
|
||||
|
||||
// Collect processor iteraries
|
||||
std::vector<Record*> ProcItinList =
|
||||
Records.getAllDerivedDefinitions("ProcessorItineraries");
|
||||
|
||||
//
|
||||
// Collect the instruction classes
|
||||
//
|
||||
for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
|
||||
Record *Proc = ProcItinList[i];
|
||||
|
||||
// Get processor itinerary name
|
||||
const std::string &Name = Proc->getName();
|
||||
|
||||
// Skip default
|
||||
if (Name == "NoItineraries")
|
||||
continue;
|
||||
|
||||
// Sanity check for at least one instruction itinerary class
|
||||
unsigned NItinClasses =
|
||||
Records.getAllDerivedDefinitions("InstrItinClass").size();
|
||||
if (NItinClasses == 0)
|
||||
return;
|
||||
|
||||
// Get itinerary data list
|
||||
std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
|
||||
|
||||
// Collect instruction classes for all itinerary data
|
||||
for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
|
||||
Record *ItinData = ItinDataList[j];
|
||||
unsigned NStages;
|
||||
collectAllInsnClasses(Name, ItinData, NStages, OS);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Run a worklist algorithm to generate the DFA
|
||||
//
|
||||
DFA D;
|
||||
State* Initial = new State;
|
||||
Initial->isInitial = true;
|
||||
Initial->stateInfo.insert(0x0);
|
||||
D.addState(Initial);
|
||||
SmallVector<State*, 32> WorkList;
|
||||
std::map<std::set<unsigned>, State*> Visited;
|
||||
|
||||
WorkList.push_back(Initial);
|
||||
|
||||
//
|
||||
// Worklist algorithm to create a DFA for processor resource tracking
|
||||
// C = {set of InsnClasses}
|
||||
// Begin with initial node in worklist. Initial node does not have
|
||||
// any consumed resources,
|
||||
// ResourceState = 0x0
|
||||
// Visited = {}
|
||||
// While worklist != empty
|
||||
// S = first element of worklist
|
||||
// For every instruction class C
|
||||
// if we can accommodate C in S:
|
||||
// S' = state with resource states = {S Union C}
|
||||
// Add a new transition: S x C -> S'
|
||||
// If S' is not in Visited:
|
||||
// Add S' to worklist
|
||||
// Add S' to Visited
|
||||
//
|
||||
while (!WorkList.empty()) {
|
||||
State* current = WorkList.pop_back_val();
|
||||
for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
|
||||
CE = allInsnClasses.end(); CI != CE; ++CI) {
|
||||
unsigned InsnClass = *CI;
|
||||
|
||||
std::set<unsigned> NewStateResources;
|
||||
//
|
||||
// If we haven't already created a transition for this input
|
||||
// and the state can accommodate this InsnClass, create a transition
|
||||
//
|
||||
if (!D.getTransition(current, InsnClass) &&
|
||||
current->canAddInsnClass(InsnClass, NewStateResources)) {
|
||||
State* NewState = NULL;
|
||||
|
||||
//
|
||||
// If we have seen this state before, then do not create a new state
|
||||
//
|
||||
//
|
||||
std::map<std::set<unsigned>, State*>::iterator VI;
|
||||
if ((VI = Visited.find(NewStateResources)) != Visited.end())
|
||||
NewState = VI->second;
|
||||
else {
|
||||
NewState = new State;
|
||||
NewState->stateInfo = NewStateResources;
|
||||
D.addState(NewState);
|
||||
Visited[NewStateResources] = NewState;
|
||||
WorkList.push_back(NewState);
|
||||
}
|
||||
|
||||
Transition* NewTransition = new Transition(current, InsnClass,
|
||||
NewState);
|
||||
D.addTransition(NewTransition);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Print out the table
|
||||
D.writeTableAndAPI(OS, TargetName);
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
//===- DFAPacketizerEmitter.h - Packetization DFA for a VLIW machine-------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This class parses the Schedule.td file and produces an API that can be used
|
||||
// to reason about whether an instruction can be added to a packet on a VLIW
|
||||
// architecture. The class internally generates a deterministic finite
|
||||
// automaton (DFA) that models all possible mappings of machine instructions
|
||||
// to functional units as instructions are added to a packet.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/ADT/DenseSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/TableGen/TableGenBackend.h"
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
namespace llvm {
|
||||
//
|
||||
// class DFAGen: class that generates and prints out the DFA for resource
|
||||
// tracking
|
||||
//
|
||||
class DFAGen : public TableGenBackend {
|
||||
private:
|
||||
std::string TargetName;
|
||||
//
|
||||
// allInsnClasses is the set of all possible resources consumed by an
|
||||
// InstrStage
|
||||
//
|
||||
DenseSet<unsigned> allInsnClasses;
|
||||
RecordKeeper &Records;
|
||||
|
||||
public:
|
||||
DFAGen(RecordKeeper& R);
|
||||
|
||||
//
|
||||
// collectAllInsnClasses: Populate allInsnClasses which is a set of units
|
||||
// used in each stage.
|
||||
//
|
||||
void collectAllInsnClasses(const std::string &Name,
|
||||
Record *ItinData,
|
||||
unsigned &NStages,
|
||||
raw_ostream &OS);
|
||||
|
||||
void run(raw_ostream &OS);
|
||||
};
|
||||
}
|
||||
|
|
@ -711,9 +711,13 @@ void SubtargetEmitter::run(raw_ostream &OS) {
|
|||
|
||||
std::string ClassName = Target + "GenSubtargetInfo";
|
||||
OS << "namespace llvm {\n";
|
||||
OS << "class DFAPacketizer;\n";
|
||||
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
|
||||
<< " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
|
||||
<< "StringRef FS);\n"
|
||||
<< "public:\n"
|
||||
<< " DFAPacketizer* createDFAPacketizer(const InstrItineraryData* IID)"
|
||||
<< " const;\n"
|
||||
<< "};\n";
|
||||
OS << "} // End llvm namespace \n";
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include "CallingConvEmitter.h"
|
||||
#include "CodeEmitterGen.h"
|
||||
#include "DAGISelEmitter.h"
|
||||
#include "DFAPacketizerEmitter.h"
|
||||
#include "DisassemblerEmitter.h"
|
||||
#include "EDEmitter.h"
|
||||
#include "FastISelEmitter.h"
|
||||
|
|
@ -47,6 +48,7 @@ enum ActionType {
|
|||
GenPseudoLowering,
|
||||
GenCallingConv,
|
||||
GenDAGISel,
|
||||
GenDFAPacketizer,
|
||||
GenFastISel,
|
||||
GenSubtarget,
|
||||
GenIntrinsic,
|
||||
|
|
@ -79,6 +81,8 @@ namespace {
|
|||
"Generate assembly instruction matcher"),
|
||||
clEnumValN(GenDAGISel, "gen-dag-isel",
|
||||
"Generate a DAG instruction selector"),
|
||||
clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
|
||||
"Generate DFA Packetizer for VLIW targets"),
|
||||
clEnumValN(GenFastISel, "gen-fast-isel",
|
||||
"Generate a \"fast\" instruction selector"),
|
||||
clEnumValN(GenSubtarget, "gen-subtarget",
|
||||
|
|
@ -134,6 +138,9 @@ public:
|
|||
case GenDAGISel:
|
||||
DAGISelEmitter(Records).run(OS);
|
||||
break;
|
||||
case GenDFAPacketizer:
|
||||
DFAGen(Records).run(OS);
|
||||
break;
|
||||
case GenFastISel:
|
||||
FastISelEmitter(Records).run(OS);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue