forked from OSchip/llvm-project
[AArch64] Standardize suffixes for LSE Atomics mnemonics (NFCI)
This NFC changeset standardizes the suffixes used for LSE Atomics instructions. It changes the existing suffixes - 'b', 'h', 's', 'd' - to the existing standard 'B', 'H', 'W' and 'X'. This changeset is the result of the code review discussion for D35319. Patch by: steleman Differential Revision: https://reviews.llvm.org/D35927 llvm-svn: 309384
This commit is contained in:
Joel Jones
parent
0b37ffbbf9
commit
08e88e8df7
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@ -90,46 +90,46 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
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// XZ/WZ for LSE can only be used when acquire semantics are not used,
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// LDOPAL WZ is an invalid opcode.
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switch (MI.getOpcode()) {
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case AArch64::CASALb:
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case AArch64::CASALh:
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case AArch64::CASALs:
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case AArch64::CASALd:
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case AArch64::SWPALb:
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case AArch64::SWPALh:
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case AArch64::SWPALs:
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case AArch64::SWPALd:
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case AArch64::LDADDALb:
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case AArch64::LDADDALh:
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case AArch64::LDADDALs:
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case AArch64::LDADDALd:
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case AArch64::LDCLRALb:
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case AArch64::LDCLRALh:
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case AArch64::LDCLRALs:
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case AArch64::LDCLRALd:
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case AArch64::LDEORALb:
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case AArch64::LDEORALh:
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case AArch64::LDEORALs:
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case AArch64::LDEORALd:
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case AArch64::LDSETALb:
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case AArch64::LDSETALh:
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case AArch64::LDSETALs:
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case AArch64::LDSETALd:
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case AArch64::LDSMINALb:
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case AArch64::LDSMINALh:
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case AArch64::LDSMINALs:
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case AArch64::LDSMINALd:
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case AArch64::LDSMAXALb:
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case AArch64::LDSMAXALh:
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case AArch64::LDSMAXALs:
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case AArch64::LDSMAXALd:
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case AArch64::LDUMINALb:
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case AArch64::LDUMINALh:
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case AArch64::LDUMINALs:
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case AArch64::LDUMINALd:
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case AArch64::LDUMAXALb:
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case AArch64::LDUMAXALh:
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case AArch64::LDUMAXALs:
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case AArch64::LDUMAXALd:
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case AArch64::CASALB:
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case AArch64::CASALH:
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case AArch64::CASALW:
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case AArch64::CASALX:
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case AArch64::SWPALB:
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case AArch64::SWPALH:
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case AArch64::SWPALW:
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case AArch64::SWPALX:
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case AArch64::LDADDALB:
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case AArch64::LDADDALH:
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case AArch64::LDADDALW:
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case AArch64::LDADDALX:
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case AArch64::LDCLRALB:
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case AArch64::LDCLRALH:
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case AArch64::LDCLRALW:
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case AArch64::LDCLRALX:
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case AArch64::LDEORALB:
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case AArch64::LDEORALH:
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case AArch64::LDEORALW:
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case AArch64::LDEORALX:
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case AArch64::LDSETALB:
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case AArch64::LDSETALH:
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case AArch64::LDSETALW:
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case AArch64::LDSETALX:
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case AArch64::LDSMINALB:
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case AArch64::LDSMINALH:
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case AArch64::LDSMINALW:
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case AArch64::LDSMINALX:
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case AArch64::LDSMAXALB:
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case AArch64::LDSMAXALH:
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case AArch64::LDSMAXALW:
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case AArch64::LDSMAXALX:
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case AArch64::LDUMINALB:
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case AArch64::LDUMINALH:
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case AArch64::LDUMINALW:
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case AArch64::LDUMINALX:
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case AArch64::LDUMAXALB:
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case AArch64::LDUMAXALH:
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case AArch64::LDUMAXALW:
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case AArch64::LDUMAXALX:
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continue;
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default:
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break;
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@ -407,57 +407,57 @@ def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch),
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Sched<[WriteAtomic]>;
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// v8.1 Atomic instructions:
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def : Pat<(atomic_load_add_8 GPR64:$Rn, GPR32:$Rs), (LDADDALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_16 GPR64:$Rn, GPR32:$Rs), (LDADDALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_32 GPR64:$Rn, GPR32:$Rs), (LDADDALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_64 GPR64:$Rn, GPR64:$Rs), (LDADDALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_8 GPR64:$Rn, GPR32:$Rs), (LDADDALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_16 GPR64:$Rn, GPR32:$Rs), (LDADDALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_32 GPR64:$Rn, GPR32:$Rs), (LDADDALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_add_64 GPR64:$Rn, GPR64:$Rs), (LDADDALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_8 GPR64:$Rn, GPR32:$Rs), (LDSETALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_16 GPR64:$Rn, GPR32:$Rs), (LDSETALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_32 GPR64:$Rn, GPR32:$Rs), (LDSETALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_64 GPR64:$Rn, GPR64:$Rs), (LDSETALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_8 GPR64:$Rn, GPR32:$Rs), (LDSETALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_16 GPR64:$Rn, GPR32:$Rs), (LDSETALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_32 GPR64:$Rn, GPR32:$Rs), (LDSETALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_or_64 GPR64:$Rn, GPR64:$Rs), (LDSETALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_8 GPR64:$Rn, GPR32:$Rs), (LDEORALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_16 GPR64:$Rn, GPR32:$Rs), (LDEORALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_32 GPR64:$Rn, GPR32:$Rs), (LDEORALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_64 GPR64:$Rn, GPR64:$Rs), (LDEORALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_8 GPR64:$Rn, GPR32:$Rs), (LDEORALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_16 GPR64:$Rn, GPR32:$Rs), (LDEORALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_32 GPR64:$Rn, GPR32:$Rs), (LDEORALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_xor_64 GPR64:$Rn, GPR64:$Rs), (LDEORALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_8 GPR64:$Rn, GPR32:$Rs), (LDSMAXALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_16 GPR64:$Rn, GPR32:$Rs), (LDSMAXALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_32 GPR64:$Rn, GPR32:$Rs), (LDSMAXALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_64 GPR64:$Rn, GPR64:$Rs), (LDSMAXALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_8 GPR64:$Rn, GPR32:$Rs), (LDSMAXALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_16 GPR64:$Rn, GPR32:$Rs), (LDSMAXALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_32 GPR64:$Rn, GPR32:$Rs), (LDSMAXALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_max_64 GPR64:$Rn, GPR64:$Rs), (LDSMAXALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_8 GPR64:$Rn, GPR32:$Rs), (LDUMAXALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_16 GPR64:$Rn, GPR32:$Rs), (LDUMAXALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_32 GPR64:$Rn, GPR32:$Rs), (LDUMAXALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_64 GPR64:$Rn, GPR64:$Rs), (LDUMAXALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_8 GPR64:$Rn, GPR32:$Rs), (LDUMAXALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_16 GPR64:$Rn, GPR32:$Rs), (LDUMAXALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_32 GPR64:$Rn, GPR32:$Rs), (LDUMAXALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umax_64 GPR64:$Rn, GPR64:$Rs), (LDUMAXALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_8 GPR64:$Rn, GPR32:$Rs), (LDSMINALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_16 GPR64:$Rn, GPR32:$Rs), (LDSMINALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_32 GPR64:$Rn, GPR32:$Rs), (LDSMINALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_64 GPR64:$Rn, GPR64:$Rs), (LDSMINALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_8 GPR64:$Rn, GPR32:$Rs), (LDSMINALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_16 GPR64:$Rn, GPR32:$Rs), (LDSMINALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_32 GPR64:$Rn, GPR32:$Rs), (LDSMINALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_min_64 GPR64:$Rn, GPR64:$Rs), (LDSMINALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_8 GPR64:$Rn, GPR32:$Rs), (LDUMINALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_16 GPR64:$Rn, GPR32:$Rs), (LDUMINALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_32 GPR64:$Rn, GPR32:$Rs), (LDUMINALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_64 GPR64:$Rn, GPR64:$Rs), (LDUMINALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_8 GPR64:$Rn, GPR32:$Rs), (LDUMINALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_16 GPR64:$Rn, GPR32:$Rs), (LDUMINALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_32 GPR64:$Rn, GPR32:$Rs), (LDUMINALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_umin_64 GPR64:$Rn, GPR64:$Rs), (LDUMINALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_8 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALb GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_16 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALh GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_32 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALs GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_64 GPR64:$Rn, GPR64:$Rold, GPR64:$Rnew), (CASALd GPR64:$Rold, GPR64:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_8 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALB GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_16 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALH GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_32 GPR64:$Rn, GPR32:$Rold, GPR32:$Rnew), (CASALW GPR32:$Rold, GPR32:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_cmp_swap_64 GPR64:$Rn, GPR64:$Rold, GPR64:$Rnew), (CASALX GPR64:$Rold, GPR64:$Rnew, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_8 GPR64:$Rn, GPR32:$Rs), (SWPALb GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_16 GPR64:$Rn, GPR32:$Rs), (SWPALh GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_32 GPR64:$Rn, GPR32:$Rs), (SWPALs GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_64 GPR64:$Rn, GPR64:$Rs), (SWPALd GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_8 GPR64:$Rn, GPR32:$Rs), (SWPALB GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_16 GPR64:$Rn, GPR32:$Rs), (SWPALH GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_32 GPR64:$Rn, GPR32:$Rs), (SWPALW GPR32:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_swap_64 GPR64:$Rn, GPR64:$Rs), (SWPALX GPR64:$Rs, GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_8 GPR64:$Rn, GPR32:$Rs), (LDADDALb (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_16 GPR64:$Rn, GPR32:$Rs), (LDADDALh (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_32 GPR64:$Rn, GPR32:$Rs), (LDADDALs (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_64 GPR64:$Rn, GPR64:$Rs), (LDADDALd (SUBXrr XZR, GPR64:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_8 GPR64:$Rn, GPR32:$Rs), (LDADDALB (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_16 GPR64:$Rn, GPR32:$Rs), (LDADDALH (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_32 GPR64:$Rn, GPR32:$Rs), (LDADDALW (SUBWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_sub_64 GPR64:$Rn, GPR64:$Rs), (LDADDALX (SUBXrr XZR, GPR64:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_8 GPR64:$Rn, GPR32:$Rs), (LDCLRALb (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_16 GPR64:$Rn, GPR32:$Rs), (LDCLRALh (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_32 GPR64:$Rn, GPR32:$Rs), (LDCLRALs (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_64 GPR64:$Rn, GPR64:$Rs), (LDCLRALd (ORNXrr XZR, GPR64:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_8 GPR64:$Rn, GPR32:$Rs), (LDCLRALB (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_16 GPR64:$Rn, GPR32:$Rs), (LDCLRALH (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_32 GPR64:$Rn, GPR32:$Rs), (LDCLRALW (ORNWrr WZR, GPR32:$Rs), GPR64sp:$Rn)>;
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def : Pat<(atomic_load_and_64 GPR64:$Rn, GPR64:$Rs), (LDCLRALX (ORNXrr XZR, GPR64:$Rs), GPR64sp:$Rn)>;
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@ -9398,10 +9398,10 @@ class BaseCAS<string order, string size, RegisterClass RC>
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}
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multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order> {
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let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseCAS<order, "b", GPR32>;
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let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseCAS<order, "h", GPR32>;
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let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseCAS<order, "", GPR32>;
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let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseCAS<order, "", GPR64>;
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let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseCAS<order, "b", GPR32>;
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let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseCAS<order, "h", GPR32>;
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let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseCAS<order, "", GPR32>;
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let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseCAS<order, "", GPR64>;
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}
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class BaseCASP<string order, string size, RegisterOperand RC>
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@ -9413,10 +9413,10 @@ class BaseCASP<string order, string size, RegisterOperand RC>
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}
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multiclass CompareAndSwapPair<bits<1> Acq, bits<1> Rel, string order> {
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let Sz = 0b00, Acq = Acq, Rel = Rel in
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def s : BaseCASP<order, "", WSeqPairClassOperand>;
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let Sz = 0b01, Acq = Acq, Rel = Rel in
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def d : BaseCASP<order, "", XSeqPairClassOperand>;
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let Sz = 0b00, Acq = Acq, Rel = Rel in
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def W : BaseCASP<order, "", WSeqPairClassOperand>;
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let Sz = 0b01, Acq = Acq, Rel = Rel in
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def X : BaseCASP<order, "", XSeqPairClassOperand>;
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}
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let Predicates = [HasLSE] in
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@ -9446,10 +9446,10 @@ class BaseSWP<string order, string size, RegisterClass RC>
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}
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multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
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let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
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let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
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let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseSWP<order, "", GPR32>;
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let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>;
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let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseSWP<order, "b", GPR32>;
|
||||
let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseSWP<order, "h", GPR32>;
|
||||
let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseSWP<order, "", GPR32>;
|
||||
let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseSWP<order, "", GPR64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
|
||||
|
|
@ -9480,14 +9480,14 @@ class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
|
|||
|
||||
multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
|
||||
string order> {
|
||||
let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def b : BaseLDOPregister<op, order, "b", GPR32>;
|
||||
let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def h : BaseLDOPregister<op, order, "h", GPR32>;
|
||||
let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def s : BaseLDOPregister<op, order, "", GPR32>;
|
||||
let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def d : BaseLDOPregister<op, order, "", GPR64>;
|
||||
let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def B : BaseLDOPregister<op, order, "b", GPR32>;
|
||||
let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def H : BaseLDOPregister<op, order, "h", GPR32>;
|
||||
let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def W : BaseLDOPregister<op, order, "", GPR32>;
|
||||
let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def X : BaseLDOPregister<op, order, "", GPR64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasLSE] in
|
||||
|
|
@ -9496,22 +9496,22 @@ class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
|
|||
InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
|
||||
|
||||
multiclass STOPregister<string asm, string instr> {
|
||||
def : BaseSTOPregister<asm # "lb", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "Lb")>;
|
||||
def : BaseSTOPregister<asm # "lh", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "Lh")>;
|
||||
def : BaseSTOPregister<asm # "l", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "Ls")>;
|
||||
def : BaseSTOPregister<asm # "l", GPR64, XZR,
|
||||
!cast<Instruction>(instr # "Ld")>;
|
||||
def : BaseSTOPregister<asm # "b", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "b")>;
|
||||
def : BaseSTOPregister<asm # "h", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "h")>;
|
||||
def : BaseSTOPregister<asm, GPR32, WZR,
|
||||
!cast<Instruction>(instr # "s")>;
|
||||
def : BaseSTOPregister<asm, GPR64, XZR,
|
||||
!cast<Instruction>(instr # "d")>;
|
||||
def : BaseSTOPregister<asm # "lb", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "LB")>;
|
||||
def : BaseSTOPregister<asm # "lh", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "LH")>;
|
||||
def : BaseSTOPregister<asm # "l", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "LW")>;
|
||||
def : BaseSTOPregister<asm # "l", GPR64, XZR,
|
||||
!cast<Instruction>(instr # "LX")>;
|
||||
def : BaseSTOPregister<asm # "b", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "B")>;
|
||||
def : BaseSTOPregister<asm # "h", GPR32, WZR,
|
||||
!cast<Instruction>(instr # "H")>;
|
||||
def : BaseSTOPregister<asm, GPR32, WZR,
|
||||
!cast<Instruction>(instr # "W")>;
|
||||
def : BaseSTOPregister<asm, GPR64, XZR,
|
||||
!cast<Instruction>(instr # "X")>;
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue