forked from OSchip/llvm-project
[AArch64][AsmParser] NFC: Parser.getTok() -> getTok()
Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D106949
This commit is contained in:
Cullen Rhodes
parent
da61ab8475
commit
08d92dbbff
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@ -2673,7 +2673,7 @@ unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
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OperandMatchResultTy
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AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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@ -2693,12 +2693,12 @@ AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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if (Parser.getTok().isNot(AsmToken::Identifier)) {
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if (getTok().isNot(AsmToken::Identifier)) {
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Error(S, "Expected cN operand where 0 <= N <= 15");
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return MatchOperand_ParseFail;
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}
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StringRef Tok = Parser.getTok().getIdentifier();
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StringRef Tok = getTok().getIdentifier();
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if (Tok[0] != 'c' && Tok[0] != 'C') {
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Error(S, "Expected cN operand where 0 <= N <= 15");
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return MatchOperand_ParseFail;
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@ -2723,7 +2723,7 @@ OperandMatchResultTy
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AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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auto LookupByName = [](StringRef N) {
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if (IsSVEPrefetch) {
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@ -2792,7 +2792,7 @@ OperandMatchResultTy
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AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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TokError("invalid operand for instruction");
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return MatchOperand_ParseFail;
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@ -2815,7 +2815,7 @@ OperandMatchResultTy
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AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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TokError("invalid operand for instruction");
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return MatchOperand_ParseFail;
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@ -2841,7 +2841,7 @@ AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
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SMLoc S = getLoc();
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const MCExpr *Expr = nullptr;
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if (Parser.getTok().is(AsmToken::Hash)) {
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if (getTok().is(AsmToken::Hash)) {
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Parser.Lex(); // Eat hash token.
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}
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@ -2894,10 +2894,10 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
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const MCExpr *Expr = nullptr;
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// Leave anything with a bracket to the default for SVE
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if (getParser().getTok().is(AsmToken::LBrac))
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if (getTok().is(AsmToken::LBrac))
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return MatchOperand_NoMatch;
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if (getParser().getTok().is(AsmToken::Hash))
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if (getTok().is(AsmToken::Hash))
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getParser().Lex(); // Eat hash token.
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if (parseSymbolicImmVal(Expr))
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@ -2935,7 +2935,7 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
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// Handle negation, as that still comes through as a separate token.
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bool isNegative = parseOptionalToken(AsmToken::Minus);
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (!Tok.is(AsmToken::Real) && !Tok.is(AsmToken::Integer)) {
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if (!Hash)
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return MatchOperand_NoMatch;
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@ -2986,16 +2986,16 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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if (Parser.getTok().is(AsmToken::Hash))
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if (getTok().is(AsmToken::Hash))
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Parser.Lex(); // Eat '#'
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else if (Parser.getTok().isNot(AsmToken::Integer))
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else if (getTok().isNot(AsmToken::Integer))
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// Operand should start from # or should be integer, emit error otherwise.
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return MatchOperand_NoMatch;
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const MCExpr *Imm = nullptr;
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if (parseSymbolicImmVal(Imm))
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return MatchOperand_ParseFail;
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else if (Parser.getTok().isNot(AsmToken::Comma)) {
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else if (getTok().isNot(AsmToken::Comma)) {
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Operands.push_back(
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AArch64Operand::CreateImm(Imm, S, getLoc(), getContext()));
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return MatchOperand_Success;
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@ -3005,8 +3005,8 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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Parser.Lex();
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// The optional operand must be "lsl #N" where N is non-negative.
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if (!Parser.getTok().is(AsmToken::Identifier) ||
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!Parser.getTok().getIdentifier().equals_insensitive("lsl")) {
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if (!getTok().is(AsmToken::Identifier) ||
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!getTok().getIdentifier().equals_insensitive("lsl")) {
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Error(getLoc(), "only 'lsl #+N' valid after immediate");
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return MatchOperand_ParseFail;
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}
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@ -3016,12 +3016,12 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
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parseOptionalToken(AsmToken::Hash);
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if (Parser.getTok().isNot(AsmToken::Integer)) {
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if (getTok().isNot(AsmToken::Integer)) {
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Error(getLoc(), "only 'lsl #+N' valid after immediate");
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return MatchOperand_ParseFail;
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}
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int64_t ShiftAmount = Parser.getTok().getIntVal();
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int64_t ShiftAmount = getTok().getIntVal();
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if (ShiftAmount < 0) {
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Error(getLoc(), "positive shift amount required");
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@ -3087,7 +3087,7 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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bool invertCondCode) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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StringRef Cond = Tok.getString();
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@ -3110,7 +3110,7 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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OperandMatchResultTy
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AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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SMLoc S = getLoc();
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if (Tok.isNot(AsmToken::Identifier)) {
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@ -3132,7 +3132,7 @@ AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
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OperandMatchResultTy
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AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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SMLoc S = getLoc();
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StringRef Name = Tok.getString();
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@ -3195,7 +3195,7 @@ AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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OperandMatchResultTy
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AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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std::string LowerID = Tok.getString().lower();
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AArch64_AM::ShiftExtendType ShOp =
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StringSwitch<AArch64_AM::ShiftExtendType>(LowerID)
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@ -3241,9 +3241,8 @@ AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
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// Make sure we do actually have a number, identifier or a parenthesized
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// expression.
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SMLoc E = getLoc();
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if (!Parser.getTok().is(AsmToken::Integer) &&
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!Parser.getTok().is(AsmToken::LParen) &&
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!Parser.getTok().is(AsmToken::Identifier)) {
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if (!getTok().is(AsmToken::Integer) && !getTok().is(AsmToken::LParen) &&
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!getTok().is(AsmToken::Identifier)) {
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Error(E, "expected integer shift amount");
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return MatchOperand_ParseFail;
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}
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@ -3365,7 +3364,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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Operands.push_back(AArch64Operand::CreateToken("sys", NameLoc, getContext()));
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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StringRef Op = Tok.getString();
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SMLoc S = Tok.getLoc();
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@ -3454,7 +3453,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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OperandMatchResultTy
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AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Mnemonic == "tsb" && Tok.isNot(AsmToken::Identifier)) {
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TokError("'csync' operand expected");
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@ -3527,7 +3526,7 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
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OperandMatchResultTy
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AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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assert(Mnemonic == "dsb" && "Instruction does not accept nXS operands");
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if (Mnemonic != "dsb")
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@ -3582,7 +3581,7 @@ AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
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OperandMatchResultTy
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AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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@ -3613,8 +3612,7 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
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/// tryParseNeonVectorRegister - Parse a vector register operand.
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bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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if (Parser.getTok().isNot(AsmToken::Identifier))
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if (getTok().isNot(AsmToken::Identifier))
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return true;
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SMLoc S = getLoc();
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@ -3676,7 +3674,7 @@ OperandMatchResultTy
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AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
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RegKind MatchKind) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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@ -3734,7 +3732,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
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// Not all predicates are followed by a '/m' or '/z'.
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MCAsmParser &Parser = getParser();
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if (Parser.getTok().isNot(AsmToken::Slash))
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if (getTok().isNot(AsmToken::Slash))
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return MatchOperand_Success;
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// But when they do they shouldn't have an element type suffix.
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@ -3749,7 +3747,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
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Parser.Lex(); // Eat the slash.
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// Zeroing or merging?
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auto Pred = Parser.getTok().getString().lower();
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auto Pred = getTok().getString().lower();
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if (Pred != "z" && Pred != "m") {
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Error(getLoc(), "expecting 'm' or 'z' predication");
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return MatchOperand_ParseFail;
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@ -3784,10 +3782,10 @@ bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
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if (parseOptionalToken(AsmToken::Colon)) {
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HasELFModifier = true;
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if (Parser.getTok().isNot(AsmToken::Identifier))
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if (getTok().isNot(AsmToken::Identifier))
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return TokError("expect relocation specifier in operand after ':'");
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std::string LowerCase = Parser.getTok().getIdentifier().lower();
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std::string LowerCase = getTok().getIdentifier().lower();
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RefKind = StringSwitch<AArch64MCExpr::VariantKind>(LowerCase)
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.Case("lo12", AArch64MCExpr::VK_LO12)
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.Case("abs_g3", AArch64MCExpr::VK_ABS_G3)
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@ -3974,13 +3972,13 @@ OperandMatchResultTy
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AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
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bool ExpectMatch) {
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MCAsmParser &Parser = getParser();
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if (!Parser.getTok().is(AsmToken::LCurly))
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if (!getTok().is(AsmToken::LCurly))
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return MatchOperand_NoMatch;
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// Wrapper around parse function
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auto ParseVector = [this, &Parser](unsigned &Reg, StringRef &Kind, SMLoc Loc,
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bool NoMatchIsError) {
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auto RegTok = Parser.getTok();
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auto ParseVector = [this](unsigned &Reg, StringRef &Kind, SMLoc Loc,
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bool NoMatchIsError) {
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auto RegTok = getTok();
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auto ParseRes = tryParseVectorRegister(Reg, Kind, VectorKind);
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if (ParseRes == MatchOperand_Success) {
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if (parseVectorKind(Kind, VectorKind))
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@ -4000,7 +3998,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
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};
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SMLoc S = getLoc();
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auto LCurly = Parser.getTok();
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auto LCurly = getTok();
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Parser.Lex(); // Eat left bracket token.
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StringRef Kind;
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@ -4117,7 +4115,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
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parseOptionalToken(AsmToken::Hash);
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if (getParser().getTok().isNot(AsmToken::Integer)) {
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if (getTok().isNot(AsmToken::Integer)) {
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Error(getLoc(), "index must be absent or #0");
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return MatchOperand_ParseFail;
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}
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@ -4145,7 +4143,7 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
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return Res;
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// No shift/extend is the default.
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if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
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if (!ParseShiftExtend || getTok().isNot(AsmToken::Comma)) {
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Operands.push_back(AArch64Operand::CreateReg(
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RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));
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return MatchOperand_Success;
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@ -4178,7 +4176,7 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
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bool NextIsVL =
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Parser.getLexer().peekTok().getString().equals_insensitive("vl");
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bool NextIsHash = Parser.getLexer().peekTok().is(AsmToken::Hash);
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if (!Parser.getTok().getString().equals_insensitive("mul") ||
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if (!getTok().getString().equals_insensitive("mul") ||
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!(NextIsVL || NextIsHash))
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return true;
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@ -4213,7 +4211,7 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
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bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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auto Tok = Parser.getTok();
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auto Tok = getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return true;
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@ -4332,7 +4330,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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// Parse a negative sign
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bool isNegative = false;
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if (Parser.getTok().is(AsmToken::Minus)) {
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if (getTok().is(AsmToken::Minus)) {
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isNegative = true;
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// We need to consume this token only when we have a Real, otherwise
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// we let parseSymbolicImmVal take care of it
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@ -4343,7 +4341,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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// The only Real that should come through here is a literal #0.0 for
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// the fcmp[e] r, #0.0 instructions. They expect raw token operands,
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// so convert the value.
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = getTok();
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if (Tok.is(AsmToken::Real)) {
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APFloat RealVal(APFloat::IEEEdouble(), Tok.getString());
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uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
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@ -4431,8 +4429,7 @@ bool AArch64AsmParser::parseImmExpr(int64_t &Out) {
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}
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bool AArch64AsmParser::parseComma() {
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if (check(getParser().getTok().isNot(AsmToken::Comma), getLoc(),
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"expected comma"))
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if (check(getTok().isNot(AsmToken::Comma), getLoc(), "expected comma"))
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return true;
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// Eat the comma
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getParser().Lex();
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@ -4507,7 +4504,6 @@ bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1,
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bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
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StringRef Name, SMLoc NameLoc,
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OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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Name = StringSwitch<StringRef>(Name.lower())
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.Case("beq", "b.eq")
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.Case("bne", "b.ne")
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@ -4530,8 +4526,8 @@ bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
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.Default(Name);
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// First check for the AArch64-specific .req directive.
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if (Parser.getTok().is(AsmToken::Identifier) &&
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Parser.getTok().getIdentifier().lower() == ".req") {
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if (getTok().is(AsmToken::Identifier) &&
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getTok().getIdentifier().lower() == ".req") {
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parseDirectiveReq(Name, NameLoc);
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// We always return 'error' for this, as we're done with this
|
||||
// statement and don't need to match the 'instruction."
|
||||
|
|
@ -6206,12 +6202,12 @@ bool AArch64AsmParser::parseDirectiveTLSDescCall(SMLoc L) {
|
|||
/// The number of arguments depends on the loh identifier.
|
||||
bool AArch64AsmParser::parseDirectiveLOH(StringRef IDVal, SMLoc Loc) {
|
||||
MCLOHType Kind;
|
||||
if (getParser().getTok().isNot(AsmToken::Identifier)) {
|
||||
if (getParser().getTok().isNot(AsmToken::Integer))
|
||||
if (getTok().isNot(AsmToken::Identifier)) {
|
||||
if (getTok().isNot(AsmToken::Integer))
|
||||
return TokError("expected an identifier or a number in directive");
|
||||
// We successfully get a numeric value for the identifier.
|
||||
// Check if it is valid.
|
||||
int64_t Id = getParser().getTok().getIntVal();
|
||||
int64_t Id = getTok().getIntVal();
|
||||
if (Id <= -1U && !isValidMCLOHType(Id))
|
||||
return TokError("invalid numeric identifier in directive");
|
||||
Kind = (MCLOHType)Id;
|
||||
|
|
@ -6332,7 +6328,7 @@ bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) {
|
|||
MCAsmParser &Parser = getParser();
|
||||
if (getTok().isNot(AsmToken::Identifier))
|
||||
return TokError("unexpected input in .unreq directive.");
|
||||
RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
|
||||
RegisterReqs.erase(getTok().getIdentifier().lower());
|
||||
Parser.Lex(); // Eat the identifier.
|
||||
return parseToken(AsmToken::EndOfStatement);
|
||||
}
|
||||
|
|
@ -6359,7 +6355,7 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() {
|
|||
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
|
||||
MCAsmParser &Parser = getParser();
|
||||
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
const AsmToken &Tok = getTok();
|
||||
if (Tok.isNot(AsmToken::Identifier))
|
||||
return TokError("expected symbol name");
|
||||
|
||||
|
|
@ -6741,7 +6737,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
|
|||
|
||||
SMLoc S = getLoc();
|
||||
|
||||
if (getParser().getTok().isNot(AsmToken::Identifier)) {
|
||||
if (getTok().isNot(AsmToken::Identifier)) {
|
||||
Error(S, "expected register");
|
||||
return MatchOperand_ParseFail;
|
||||
}
|
||||
|
|
@ -6773,7 +6769,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
|
|||
return MatchOperand_ParseFail;
|
||||
}
|
||||
|
||||
if (getParser().getTok().isNot(AsmToken::Comma)) {
|
||||
if (getTok().isNot(AsmToken::Comma)) {
|
||||
Error(getLoc(), "expected comma");
|
||||
return MatchOperand_ParseFail;
|
||||
}
|
||||
|
|
@ -6833,7 +6829,7 @@ AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
|
|||
unsigned ElementWidth = KindRes->second;
|
||||
|
||||
// No shift/extend is the default.
|
||||
if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
|
||||
if (!ParseShiftExtend || getTok().isNot(AsmToken::Comma)) {
|
||||
Operands.push_back(AArch64Operand::CreateVectorReg(
|
||||
RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext()));
|
||||
|
||||
|
|
@ -6866,7 +6862,7 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
|
|||
MCAsmParser &Parser = getParser();
|
||||
|
||||
SMLoc SS = getLoc();
|
||||
const AsmToken &TokE = Parser.getTok();
|
||||
const AsmToken &TokE = getTok();
|
||||
bool IsHash = TokE.is(AsmToken::Hash);
|
||||
|
||||
if (!IsHash && TokE.isNot(AsmToken::Identifier))
|
||||
|
|
|
|||
Loading…
Reference in New Issue