From 08b81a5508473eecb3b12d7d621962b16fdada6e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Tue, 10 Jul 2018 06:19:54 +0000
Subject: [PATCH] [X86] Use IsProfitableToFold to block vinsertf128rm in favor
 of insert_subreg instead of artifically increasing pattern complexity to give
 priority.

This is a much more direct way to solve the issue than just giving extra priority.

llvm-svn: 336639
---
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp    | 5 +++++
 llvm/lib/Target/X86/X86InstrVecCompiler.td | 1 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index c7120cf3673f..3b903dafe2c0 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -614,6 +614,11 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
     }
   }
 
+  // Prevent folding a load if this can implemented with an insert_subreg.
+  if (Root->getOpcode() == ISD::INSERT_SUBVECTOR &&
+      Root->getOperand(0).isUndef() && isNullConstant(Root->getOperand(2)))
+    return false;
+
   return true;
 }
 
diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td
index 6f0bf4bd5fc5..30e467c55f1d 100644
--- a/llvm/lib/Target/X86/X86InstrVecCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td
@@ -147,7 +147,6 @@ multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
   def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
             (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
 
-  let AddedComplexity = 25 in // to give priority over vinsertf128rm
   def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
             (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
 }