From 08b4a50e39d8b8db17b8eddacba795e99304e418 Mon Sep 17 00:00:00 2001 From: Amy Kwan Date: Wed, 22 Jul 2020 12:16:08 -0500 Subject: [PATCH] [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation The implementation of the xvtlsbb builtins/intrinsics were not correct as the intrinsics previously used i1 as an argument type. This patch changes the i1 argument type used in these intrinsics to be i32 instead, as having the second as an i1 can lead to issues in the backend. Differential Revision: https://reviews.llvm.org/D84291 --- clang/include/clang/Basic/BuiltinsPPC.def | 2 +- clang/test/CodeGen/builtins-ppc-p10vector.c | 4 ++-- llvm/include/llvm/IR/IntrinsicsPowerPC.td | 2 +- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 2 +- llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll | 9 ++++++--- 5 files changed, 11 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 5d445c253a85..b74cb8df78ba 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -467,7 +467,7 @@ BUILTIN(__builtin_vsx_xxsldwi, "v.", "t") BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "") -BUILTIN(__builtin_vsx_xvtlsbb, "iV16Ucb", "") +BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "") // P10 Vector Permute Extended built-in. BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "") diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c index 4e804fbafb30..0d084c6eed85 100644 --- a/clang/test/CodeGen/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/builtins-ppc-p10vector.c @@ -583,13 +583,13 @@ vector float test_vec_vec_splati_ins_f(void) { } int test_vec_test_lsbb_all_ones(void) { - // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 true + // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1 // CHECK-NEXT: ret i32 return vec_test_lsbb_all_ones(vuca); } int test_vec_test_lsbb_all_zeros(void) { - // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 false + // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 0 // CHECK-NEXT: ret i32 return vec_test_lsbb_all_zeros(vuca); } diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 2abb6b4e55fe..d2d418bc2d64 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -1069,7 +1069,7 @@ def int_ppc_vsx_xxinsertw : [IntrNoMem]>; def int_ppc_vsx_xvtlsbb : PowerPC_VSX_Intrinsic<"xvtlsbb", [llvm_i32_ty], - [llvm_v16i8_ty, llvm_i1_ty], [IntrNoMem]>; + [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; def int_ppc_vsx_xxeval : PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index 6bf8475a7947..4c9f9e8bb083 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -1085,7 +1085,7 @@ let Predicates = [IsISA3_1] in { (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; - def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)), + def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll index d4e71d18c6eb..2ac1b2b7514b 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll @@ -2,11 +2,14 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s ; These test cases aims to test the builtins for the Power10 VSX vector ; instructions introduced in ISA 3.1. -declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1) +declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i32) define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) { ; CHECK-LABEL: test_vec_test_lsbb_all_ones: @@ -17,7 +20,7 @@ define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) { ; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: blr entry: - %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 1) + %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1) ret i32 %0 } @@ -30,6 +33,6 @@ define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) { ; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: blr entry: - %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i1 0) + %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 0) ret i32 %0 }