forked from OSchip/llvm-project
[AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics that
use f32/f64 types, rather than their vector equivalents. llvm-svn: 197068
This commit is contained in:
Chad Rosier
parent
473a01e1c9
commit
088f93d4b5
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@ -282,35 +282,50 @@ def int_aarch64_neon_vrsqrts :
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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class Neon_Cmp_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyvector_ty],
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[IntrNoMem]>;
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// Compare with vector operands.
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class Neon_Cmp_Intrinsic :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyvector_ty],
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[IntrNoMem]>;
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// Floating-point compare with scalar operands.
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class Neon_Float_Cmp_Intrinsic :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_anyfloat_ty],
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[IntrNoMem]>;
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// Scalar Compare Equal
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def int_aarch64_neon_vceq : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fceq : Neon_Float_Cmp_Intrinsic;
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// Scalar Compare Greater-Than or Equal
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def int_aarch64_neon_vcge : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_vchs : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fcge : Neon_Float_Cmp_Intrinsic;
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def int_aarch64_neon_fchs : Neon_Float_Cmp_Intrinsic;
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// Scalar Compare Less-Than or Equal
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def int_aarch64_neon_vclez : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fclez : Neon_Float_Cmp_Intrinsic;
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// Scalar Compare Less-Than
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def int_aarch64_neon_vcltz : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fcltz : Neon_Float_Cmp_Intrinsic;
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// Scalar Compare Greater-Than
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def int_aarch64_neon_vcgt : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_vchi : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fcgt : Neon_Float_Cmp_Intrinsic;
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def int_aarch64_neon_fchi : Neon_Float_Cmp_Intrinsic;
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// Scalar Compare Bitwise Test Bits
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def int_aarch64_neon_vtstd : Neon_Cmp_Intrinsic;
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// Scalar Floating-point Absolute Compare Greater Than Or Equal
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def int_aarch64_neon_vcage : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fcage : Neon_Float_Cmp_Intrinsic;
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// Scalar Floating-point Absolute Compare Greater Than
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def int_aarch64_neon_vcagt : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_fcagt : Neon_Float_Cmp_Intrinsic;
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// Scalar Signed Saturating Accumulated of Unsigned Value
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def int_aarch64_neon_vuqadd : Neon_2Arg_Intrinsic;
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@ -4201,9 +4201,9 @@ multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
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multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
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def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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@ -4396,11 +4396,9 @@ class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
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multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
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(v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
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def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
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(INSTS FPR32:$Rn, fpz32:$FPImm)>;
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def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
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(v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
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def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
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(INSTD FPR64:$Rn, fpz32:$FPImm)>;
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}
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@ -5163,58 +5161,62 @@ def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
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// Scalar Floating-point Compare Mask Equal
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defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fceq,
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FCMEQsss, FCMEQddd>;
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def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
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// Scalar Floating-point Compare Mask Equal To Zero
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defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq,
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FCMEQZssi, FCMEQZddi>;
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def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
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(FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
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// Scalar Floating-point Compare Mask Greater Than Or Equal
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defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcge,
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FCMGEsss, FCMGEddd>;
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def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
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// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
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defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge,
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FCMGEZssi, FCMGEZddi>;
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// Scalar Floating-point Compare Mask Greather Than
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defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcgt,
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FCMGTsss, FCMGTddd>;
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def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
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// Scalar Floating-point Compare Mask Greather Than Zero
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defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt,
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FCMGTZssi, FCMGTZddi>;
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// Scalar Floating-point Compare Mask Less Than Or Equal To Zero
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defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez,
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FCMLEZssi, FCMLEZddi>;
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// Scalar Floating-point Compare Mask Less Than Zero
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defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz,
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FCMLTZssi, FCMLTZddi>;
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// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
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defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcage,
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FACGEsss, FACGEddd>;
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def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FACGEddd FPR64:$Rn, FPR64:$Rm)>;
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// Scalar Floating-point Absolute Compare Mask Greater Than
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defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcagt,
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FACGTsss, FACGTddd>;
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def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FACGTddd FPR64:$Rn, FPR64:$Rm)>;
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// Scakar Floating-point Absolute Difference
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defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
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@ -3,29 +3,25 @@
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;; Scalar Floating-point Compare
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define i32 @test_vceqs_f32(float %a, float %b) {
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; CHECK: test_vceqs_f32
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; CHECK-LABEL: test_vceqs_f32
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; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vceq.i = insertelement <1 x float> undef, float %a, i32 0
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%vceq1.i = insertelement <1 x float> undef, float %b, i32 0
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%vceq2.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> %vceq1.i)
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%0 = extractelement <1 x i32> %vceq2.i, i32 0
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%fceq2.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float %b)
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%0 = extractelement <1 x i32> %fceq2.i, i32 0
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ret i32 %0
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}
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define i64 @test_vceqd_f64(double %a, double %b) {
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; CHECK: test_vceqd_f64
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; CHECK-LABEL: test_vceqd_f64
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; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vceq.i = insertelement <1 x double> undef, double %a, i32 0
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%vceq1.i = insertelement <1 x double> undef, double %b, i32 0
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%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> %vceq1.i)
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%0 = extractelement <1 x i64> %vceq2.i, i32 0
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%fceq2.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double %a, double %b)
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%0 = extractelement <1 x i64> %fceq2.i, i32 0
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ret i64 %0
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}
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define <1 x i64> @test_vceqz_f64(<1 x double> %a) #0 {
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; CHECK: test_vceqz_f64
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define <1 x i64> @test_vceqz_f64(<1 x double> %a) {
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; CHECK-LABEL: test_vceqz_f64
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; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0
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entry:
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%0 = fcmp oeq <1 x double> %a, zeroinitializer
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@ -34,295 +30,253 @@ entry:
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}
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define i32 @test_vceqzs_f32(float %a) {
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; CHECK: test_vceqzs_f32
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; CHECK-LABEL: test_vceqzs_f32
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; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
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entry:
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%vceq.i = insertelement <1 x float> undef, float %a, i32 0
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%vceq1.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> zeroinitializer)
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%0 = extractelement <1 x i32> %vceq1.i, i32 0
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%fceq1.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float 0.0)
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%0 = extractelement <1 x i32> %fceq1.i, i32 0
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ret i32 %0
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}
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define i64 @test_vceqzd_f64(double %a) {
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; CHECK: test_vceqzd_f64
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; CHECK-LABEL: test_vceqzd_f64
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; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
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entry:
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%vceq.i = insertelement <1 x double> undef, double %a, i32 0
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%vceq1.i = tail call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double> %vceq.i, <1 x float> zeroinitializer) #5
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%0 = extractelement <1 x i64> %vceq1.i, i32 0
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%fceq1.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double %a, float 0.0)
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%0 = extractelement <1 x i64> %fceq1.i, i32 0
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ret i64 %0
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}
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define i32 @test_vcges_f32(float %a, float %b) {
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; CHECK: test_vcges_f32
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; CHECK-LABEL: test_vcges_f32
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; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcge.i = insertelement <1 x float> undef, float %a, i32 0
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%vcge1.i = insertelement <1 x float> undef, float %b, i32 0
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%vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
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%0 = extractelement <1 x i32> %vcge2.i, i32 0
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%fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
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%0 = extractelement <1 x i32> %fcge2.i, i32 0
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ret i32 %0
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}
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define i64 @test_vcged_f64(double %a, double %b) {
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; CHECK: test_vcged_f64
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; CHECK-LABEL: test_vcged_f64
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; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcge.i = insertelement <1 x double> undef, double %a, i32 0
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%vcge1.i = insertelement <1 x double> undef, double %b, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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%fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
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%0 = extractelement <1 x i64> %fcge2.i, i32 0
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ret i64 %0
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}
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define i32 @test_vcgezs_f32(float %a) {
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; CHECK: test_vcgezs_f32
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; CHECK-LABEL: test_vcgezs_f32
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; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, #0.0
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entry:
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%vcge.i = insertelement <1 x float> undef, float %a, i32 0
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%vcge1.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> zeroinitializer)
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%0 = extractelement <1 x i32> %vcge1.i, i32 0
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%fcge1.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float 0.0)
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%0 = extractelement <1 x i32> %fcge1.i, i32 0
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ret i32 %0
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}
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define i64 @test_vcgezd_f64(double %a) {
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; CHECK: test_vcgezd_f64
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; CHECK-LABEL: test_vcgezd_f64
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; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
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entry:
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%vcge.i = insertelement <1 x double> undef, double %a, i32 0
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%vcge1.i = tail call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double> %vcge.i, <1 x float> zeroinitializer) #5
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%0 = extractelement <1 x i64> %vcge1.i, i32 0
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%fcge1.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double %a, float 0.0)
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%0 = extractelement <1 x i64> %fcge1.i, i32 0
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ret i64 %0
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}
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define i32 @test_vcgts_f32(float %a, float %b) {
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; CHECK: test_vcgts_f32
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; CHECK-LABEL: test_vcgts_f32
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; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcgt.i = insertelement <1 x float> undef, float %a, i32 0
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%vcgt1.i = insertelement <1 x float> undef, float %b, i32 0
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%vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
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%0 = extractelement <1 x i32> %vcgt2.i, i32 0
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%fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcgt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcgtd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcgtd_f64
|
||||
; CHECK-LABEL: test_vcgtd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
|
||||
%0 = extractelement <1 x i64> %vcgt2.i, i32 0
|
||||
%fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcgt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcgtzs_f32(float %a) {
|
||||
; CHECK: test_vcgtzs_f32
|
||||
; CHECK-LABEL: test_vcgtzs_f32
|
||||
; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcgt1.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vcgt1.i, i32 0
|
||||
%fcgt1.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float 0.0)
|
||||
%0 = extractelement <1 x i32> %fcgt1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcgtzd_f64(double %a) {
|
||||
; CHECK: test_vcgtzd_f64
|
||||
; CHECK-LABEL: test_vcgtzd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double> %vcgt.i, <1 x float> zeroinitializer) #5
|
||||
%0 = extractelement <1 x i64> %vcgt1.i, i32 0
|
||||
%fcgt1.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double %a, float 0.0)
|
||||
%0 = extractelement <1 x i64> %fcgt1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcles_f32(float %a, float %b) {
|
||||
; CHECK: test_vcles_f32
|
||||
; CHECK-LABEL: test_vcles_f32
|
||||
; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcge1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
|
||||
%0 = extractelement <1 x i32> %vcge2.i, i32 0
|
||||
%fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcge2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcled_f64(double %a, double %b) {
|
||||
; CHECK: test_vcled_f64
|
||||
; CHECK-LABEL: test_vcled_f64
|
||||
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcge1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
|
||||
%0 = extractelement <1 x i64> %vcge2.i, i32 0
|
||||
%fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcge2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vclezs_f32(float %a) {
|
||||
; CHECK: test_vclezs_f32
|
||||
; CHECK-LABEL: test_vclezs_f32
|
||||
; CHECK: fcmle {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcle.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcle1.i = call <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float> %vcle.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vcle1.i, i32 0
|
||||
%fcle1.i = call <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float %a, float 0.0)
|
||||
%0 = extractelement <1 x i32> %fcle1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vclezd_f64(double %a) {
|
||||
; CHECK: test_vclezd_f64
|
||||
; CHECK-LABEL: test_vclezd_f64
|
||||
; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcle.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcle1.i = tail call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double> %vcle.i, <1 x float> zeroinitializer) #5
|
||||
%0 = extractelement <1 x i64> %vcle1.i, i32 0
|
||||
%fcle1.i = call <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double %a, float 0.0)
|
||||
%0 = extractelement <1 x i64> %fcle1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vclts_f32(float %a, float %b) {
|
||||
; CHECK: test_vclts_f32
|
||||
; CHECK-LABEL: test_vclts_f32
|
||||
; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcgt1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
|
||||
%0 = extractelement <1 x i32> %vcgt2.i, i32 0
|
||||
%fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcgt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcltd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcltd_f64
|
||||
; CHECK-LABEL: test_vcltd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcgt1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
|
||||
%0 = extractelement <1 x i64> %vcgt2.i, i32 0
|
||||
%fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcgt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcltzs_f32(float %a) {
|
||||
; CHECK: test_vcltzs_f32
|
||||
; CHECK-LABEL: test_vcltzs_f32
|
||||
; CHECK: fcmlt {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vclt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vclt1.i = call <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float> %vclt.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vclt1.i, i32 0
|
||||
%fclt1.i = call <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float %a, float 0.0)
|
||||
%0 = extractelement <1 x i32> %fclt1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcltzd_f64(double %a) {
|
||||
; CHECK: test_vcltzd_f64
|
||||
; CHECK-LABEL: test_vcltzd_f64
|
||||
; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vclt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vclt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double> %vclt.i, <1 x float> zeroinitializer) #5
|
||||
%0 = extractelement <1 x i64> %vclt1.i, i32 0
|
||||
%fclt1.i = call <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double %a, float 0.0)
|
||||
%0 = extractelement <1 x i64> %fclt1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcages_f32(float %a, float %b) {
|
||||
; CHECK: test_vcages_f32
|
||||
; CHECK-LABEL: test_vcages_f32
|
||||
; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcage1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
|
||||
%0 = extractelement <1 x i32> %vcage2.i, i32 0
|
||||
%fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcage2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaged_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaged_f64
|
||||
; CHECK-LABEL: test_vcaged_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcage1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
|
||||
%0 = extractelement <1 x i64> %vcage2.i, i32 0
|
||||
%fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcage2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcagts_f32(float %a, float %b) {
|
||||
; CHECK: test_vcagts_f32
|
||||
; CHECK-LABEL: test_vcagts_f32
|
||||
; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcagt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcagt1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcagt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcagt.i, <1 x float> %vcagt1.i)
|
||||
%0 = extractelement <1 x i32> %vcagt2.i, i32 0
|
||||
%fcagt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcagt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcagtd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcagtd_f64
|
||||
; CHECK-LABEL: test_vcagtd_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcagt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcagt1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcagt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcagt.i, <1 x double> %vcagt1.i)
|
||||
%0 = extractelement <1 x i64> %vcagt2.i, i32 0
|
||||
%fcagt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcagt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcales_f32(float %a, float %b) {
|
||||
; CHECK: test_vcales_f32
|
||||
; CHECK-LABEL: test_vcales_f32
|
||||
; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcage1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
|
||||
%0 = extractelement <1 x i32> %vcage2.i, i32 0
|
||||
%fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcage2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaled_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaled_f64
|
||||
; CHECK-LABEL: test_vcaled_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcage1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
|
||||
%0 = extractelement <1 x i64> %vcage2.i, i32 0
|
||||
%fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcage2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcalts_f32(float %a, float %b) {
|
||||
; CHECK: test_vcalts_f32
|
||||
; CHECK-LABEL: test_vcalts_f32
|
||||
; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcalt.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcalt1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcalt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcalt.i, <1 x float> %vcalt1.i)
|
||||
%0 = extractelement <1 x i32> %vcalt2.i, i32 0
|
||||
%fcalt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
|
||||
%0 = extractelement <1 x i32> %fcalt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaltd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaltd_f64
|
||||
; CHECK-LABEL: test_vcaltd_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcalt.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcalt1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcalt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcalt.i, <1 x double> %vcalt1.i)
|
||||
%0 = extractelement <1 x i64> %vcalt2.i, i32 0
|
||||
%fcalt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
|
||||
%0 = extractelement <1 x i64> %fcalt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double, double)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double, double)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double, float)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double, double)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double, float)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double, double)
|
||||
declare <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float, float)
|
||||
declare <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double, double)
|
||||
|
|
|
|||
Loading…
Reference in New Issue