forked from OSchip/llvm-project
Fix ARM tests to be register allocator independent.
llvm-svn: 128680
This commit is contained in:
parent
6ffe738f24
commit
0888bcf542
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@ -1,4 +1,6 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=linearscan | FileCheck %s
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; This test depends on linear scan's reserved register coalescing.
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@.str = private constant [1 x i8] zeroinitializer, align 1
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@ -14,7 +14,7 @@ define i32 @f1(i32 %a, i64 %b) {
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define i32 @f2() nounwind optsize {
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; ELF: f2:
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; ELF: mov [[REGISTER:(r[0-9]+)]], #128
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; ELF: str [[REGISTER]], [sp]
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; ELF: str [[REGISTER]], [
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; DARWIN: f2:
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; DARWIN: mov r3, #128
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entry:
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@ -26,9 +26,9 @@ tailrecurse: ; preds = %sw.bb, %entry
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; ARM: ands r12, r12, #3
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; ARM-NEXT: beq
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; THUMB: movs r5, #3
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; THUMB-NEXT: ands r5, r4
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; THUMB-NEXT: cmp r5, #0
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; THUMB: movs r[[R0:[0-9]+]], #3
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; THUMB-NEXT: ands r[[R0]], r
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; THUMB-NEXT: cmp r[[R0]], #0
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; THUMB-NEXT: beq
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; T2: ands r12, r12, #3
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@ -1,8 +1,11 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=linearscan | FileCheck %s
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; rdar://8015977
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; rdar://8020118
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; This test needs the reserved register r7 to be coalesced into the ldr.
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; So far, only linear scan can do that.
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define i8* @rt0(i32 %x) nounwind readnone {
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entry:
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; CHECK: rt0:
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@ -16,7 +19,7 @@ define i8* @rt2() nounwind readnone {
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entry:
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; CHECK: rt2:
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; CHECK: {r7, lr}
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; CHECK: ldr r0, [r7]
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; CHECK: ldr r[[R0:[0-9]+]], [r7]
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; CHECK: ldr r0, [r0]
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; CHECK: ldr r0, [r0, #4]
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%0 = tail call i8* @llvm.returnaddress(i32 2)
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@ -1,6 +1,7 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8
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define float @t1(float %acc, float %a, float %b) nounwind {
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entry:
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@ -11,8 +12,8 @@ entry:
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; NEON: vnmla.f32
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; A8: t1:
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; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}}
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; A8: vsub.f32 d0, d0, d1
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; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fsub float -0.0, %0
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%2 = fsub float %1, %acc
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@ -28,8 +29,8 @@ entry:
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; NEON: vnmla.f32
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; A8: t2:
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; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}}
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; A8: vsub.f32 d0, d0, d1
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; A8: vnmul.f32 s{{[0123]}}, s{{[0123]}}, s{{[0123]}}
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; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fmul float -1.0, %0
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%2 = fsub float %1, %acc
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@ -45,8 +46,8 @@ entry:
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; NEON: vnmla.f64
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; A8: t3:
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; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d16, d16, d17
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; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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%0 = fmul double %a, %b
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%1 = fsub double -0.0, %0
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%2 = fsub double %1, %acc
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@ -62,8 +63,8 @@ entry:
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; NEON: vnmla.f64
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; A8: t4:
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; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d16, d16, d17
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; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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%0 = fmul double %a, %b
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%1 = fmul double -1.0, %0
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%2 = fsub double %1, %acc
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@ -14,15 +14,15 @@ entry:
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%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
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; indirect branch gets duplicated here
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; ARM: bx
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; THUMB: mov pc, r1
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; THUMB2: mov pc, r2
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; THUMB: mov pc,
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; THUMB2: mov pc,
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br i1 %1, label %bb3, label %bb2
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bb2: ; preds = %entry, %bb3
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%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
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; ARM: bx
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; THUMB: mov pc, r1
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; THUMB2: mov pc, r2
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; THUMB: mov pc,
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; THUMB2: mov pc,
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indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
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bb3: ; preds = %entry
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@ -1,19 +1,21 @@
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; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
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; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
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; rdar://r6949835
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; Magic ARM pair hints works best with linearscan.
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@b = external global i64*
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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;V6: ldrd r2, [r2]
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;V5: ldr r3, [r2]
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;V5: ldr r2, [r2, #4]
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;V5: ldr r{{[0-9]+}}, [r2]
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;V5: ldr r{{[0-9]+}}, [r2, #4]
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;EABI: ldr r3, [r2]
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;EABI: ldr r2, [r2, #4]
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;EABI: ldr r{{[0-9]+}}, [r2]
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;EABI: ldr r{{[0-9]+}}, [r2, #4]
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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@ -1,9 +1,13 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldmia
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; RUN: llc < %s -mtriple=arm-apple-darwin | grep stmia
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; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrb
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; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrh
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s
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%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
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; The ARM magic hinting works best with linear scan.
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; CHECK: ldmia
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; CHECK: stmia
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; CHECK: ldrh
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; CHECK: ldrb
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%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
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@src = external global %struct.x
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@dst = external global %struct.x
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@ -1,8 +1,11 @@
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=linearscan | FileCheck %s
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; vmov s0, r0 + vmov r0, s0 should have been optimized away.
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; rdar://9104514
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; Peephole leaves a dead vmovsr instruction behind, and depends on linear scan
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; to remove it.
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define void @t(float %x) nounwind ssp {
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entry:
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; CHECK: t:
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s
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; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
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%struct.int16x8_t = type { <8 x i16> }
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return2:
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; CHECK: %return2
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; CHECK: vadd.i32
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; CHECK: vmov q9, q11
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; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK-NOT: vmov
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; CHECK: vst2.32 {d16, d17, d18, d19}
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; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}}
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%tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
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%tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
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%tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1]
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define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
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; CHECK: t5:
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; CHECK: vldmia
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; CHECK: vmov q9, q8
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; How can FileCheck match Q and D registers? We need a lisp interpreter.
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; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}}
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; CHECK-NOT: vmov
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; CHECK: vld2.16 {d16[1], d18[1]}, [r0]
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; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
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; CHECK-NOT: vmov
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; CHECK: vadd.i16
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%tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1]
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@ -154,8 +156,8 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
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define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
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; CHECK: t6:
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; CHECK: vldr.64
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; CHECK: vmov d17, d16
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; CHECK-NEXT: vld2.8 {d16[1], d17[1]}
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; CHECK: vmov d[[D0:[0-9]+]], d[[D1:[0-9]+]]
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; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}
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%tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2]
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%tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]
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; CHECK: t7:
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; CHECK: vld2.32
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; CHECK: vst2.32
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; CHECK: vld1.32 {d16, d17},
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; CHECK: vmov q9, q8
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; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},
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; CHECK: vmov q[[Q0:[0-9]+]], q[[Q1:[0-9]+]]
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; CHECK-NOT: vmov
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; CHECK: vuzp.32 q8, q9
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; CHECK: vuzp.32 q[[Q1]], q[[Q0]]
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; CHECK: vst1.32
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%0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2]
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%1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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@ -271,7 +273,7 @@ define arm_aapcs_vfpcc i32 @t10() nounwind {
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entry:
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; CHECK: t10:
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; CHECK: vmul.f32 q8, q8, d0[0]
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; CHECK: vmov.i32 q9, #0x3F000000
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; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3F000000
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; CHECK: vadd.f32 q8, q8, q8
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%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
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@ -1,4 +1,7 @@
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; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=linearscan | FileCheck %s
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; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s
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; The greedy register allocator uses a single CSR here, invalidating the test.
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@b = external global i64*
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
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; rdar://8819685
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@__bar = external hidden global i8*
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%0 = load i8** @__bar, align 4
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%1 = icmp eq i8* %0, null
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br i1 %1, label %bb1, label %bb3
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; CHECK: bne
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bb1:
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store i32 1026, i32* %size, align 4
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%2 = alloca [1026 x i8], align 1
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; CHECK: mov r0, sp
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; CHECK: adds r4, r0, r4
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; CHECK: mov [[R0:r[0-9]+]], sp
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; CHECK: adds {{r[0-9]+}}, [[R0]], {{r[0-9]+}}
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%3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0
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%4 = call i32 @_called_func(i8* %3, i32* %size) nounwind
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%5 = icmp eq i32 %4, 0
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
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define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vcgts8:
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@ -161,9 +162,9 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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; rdar://7923010
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define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vcgt_zext:
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;CHECK: vmov.i32 q10, #0x1
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;CHECK: vcgt.f32 q8
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;CHECK: vand q8, q8, q10
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;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
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;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
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;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
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define void @test(float* %P, double* %D) {
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%A = load float* %P ; <float> [#uses=1]
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@ -39,10 +40,10 @@ define void @test_add(float* %P, double* %D) {
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define void @test_ext_round(float* %P, double* %D) {
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;CHECK: test_ext_round:
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%a = load float* %P ; <float> [#uses=1]
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;CHECK: vcvt.f32.f64
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;CHECK: vcvt.f64.f32
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%b = fpext float %a to double ; <double> [#uses=1]
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%A = load double* %D ; <double> [#uses=1]
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;CHECK: vcvt.f32.f64
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%B = fptrunc double %A to float ; <float> [#uses=1]
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store double %b, double* %D
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store float %B, float* %P
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
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define <8 x i8> @vld1i8(i8* %A) nounwind {
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;CHECK: vld1i8:
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@ -19,7 +20,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind {
|
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;Check for a post-increment updating load.
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||||
define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
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||||
;CHECK: vld1i16_update:
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||||
;CHECK: vld1.16 {d16}, [r1]!
|
||||
;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
|
||||
%A = load i16** %ptr
|
||||
%tmp0 = bitcast i16* %A to i8*
|
||||
%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
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||||
|
@ -39,7 +40,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind {
|
|||
;Check for a post-increment updating load with register increment.
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||||
define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
|
||||
;CHECK: vld1i32_update:
|
||||
;CHECK: vld1.32 {d16}, [r2], r1
|
||||
;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
|
||||
%A = load i32** %ptr
|
||||
%tmp0 = bitcast i32* %A to i8*
|
||||
%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
|
||||
|
@ -75,7 +76,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind {
|
|||
;Check for a post-increment updating load.
|
||||
define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
|
||||
;CHECK: vld1Qi8_update:
|
||||
;CHECK: vld1.8 {d16, d17}, [r1, :64]!
|
||||
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}, :64]!
|
||||
%A = load i8** %ptr
|
||||
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
|
||||
%tmp2 = getelementptr i8* %A, i32 16
|
||||
|
|
|
@ -1,4 +1,5 @@
|
|||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
|
||||
|
||||
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
|
||||
%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
|
||||
|
@ -36,7 +37,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
|
|||
;Check for a post-increment updating load with register increment.
|
||||
define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
|
||||
;CHECK: vld3i16_update:
|
||||
;CHECK: vld3.16 {d16, d17, d18}, [r2], r1
|
||||
;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
|
||||
%A = load i16** %ptr
|
||||
%tmp0 = bitcast i16* %A to i8*
|
||||
%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
|
||||
|
@ -121,8 +122,8 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind {
|
|||
;Check for a post-increment updating load.
|
||||
define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
|
||||
;CHECK: vld3Qi32_update:
|
||||
;CHECK: vld3.32 {d16, d18, d20}, [r1]!
|
||||
;CHECK: vld3.32 {d17, d19, d21}, [r1]!
|
||||
;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
|
||||
;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
|
||||
%A = load i32** %ptr
|
||||
%tmp0 = bitcast i32* %A to i8*
|
||||
%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
|
||||
|
|
|
@ -1,4 +1,5 @@
|
|||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
|
||||
|
||||
define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vld1lanei8:
|
||||
|
@ -279,7 +280,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
|
|||
;Check for a post-increment updating load with register increment.
|
||||
define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
|
||||
;CHECK: vld3laneQi16_update:
|
||||
;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r2], r1
|
||||
;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
|
||||
%A = load i16** %ptr
|
||||
%tmp0 = bitcast i16* %A to i8*
|
||||
%tmp1 = load <8 x i16>* %B
|
||||
|
|
Loading…
Reference in New Issue