forked from OSchip/llvm-project
[AArch64][SVE2] Asm: support TBL/TBX instructions
Summary: A three sources variant of the TBL instruction is added to the existing SVE instruction in SVE2. This is implemented with minor changes to the existing TableGen class. TBX is a new instruction with its own definition. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62600 llvm-svn: 362214
This commit is contained in:
Cullen Rhodes
parent
2e870011b6
commit
087d1337f8
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@ -1367,6 +1367,10 @@ let Predicates = [HasSVE2] in {
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defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
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defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
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defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
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// SVE table lookup (three sources)
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defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
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defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
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}
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let Predicates = [HasSVE2AES] in {
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@ -700,8 +700,8 @@ multiclass sve_int_perm_dup_i<string asm> {
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(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
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}
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class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterOperand VecList>
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class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm,
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ZPRRegOp zprty, RegisterOperand VecList>
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: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"",
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@ -713,16 +713,18 @@ class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-10} = 0b001100;
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let Inst{15-13} = 0b001;
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let Inst{12-11} = opc;
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let Inst{10} = 0b0;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_perm_tbl<string asm> {
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def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>;
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def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>;
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def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>;
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def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>;
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def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>;
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def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>;
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def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>;
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def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>;
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def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
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(!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
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@ -734,6 +736,37 @@ multiclass sve_int_perm_tbl<string asm> {
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(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
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}
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multiclass sve2_int_perm_tbl<string asm> {
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def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>;
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def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>;
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def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>;
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def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>;
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}
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class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zm;
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bits<5> Zn;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-10} = 0b001011;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve2_int_perm_tbx<string asm> {
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def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>;
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def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>;
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def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>;
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def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>;
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}
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class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn),
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asm, "\t$Zd, $Zn",
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@ -0,0 +1,51 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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tbl z0.b, { z1.b, z2.b }, z3.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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tbl z0.d, { }, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: tbl z0.d, { }, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z2.b }, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z21.d }, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { v0.2d, v1.2d }, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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tbl z28.b, { z29.b, z30.b }, z31.b
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// CHECK-INST: tbl z28.b, { z29.b, z30.b }, z31.b
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// CHECK-ENCODING: [0xbc,0x2b,0x3f,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: bc 2b 3f 05 <unknown>
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tbl z28.h, { z29.h, z30.h }, z31.h
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// CHECK-INST: tbl z28.h, { z29.h, z30.h }, z31.h
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// CHECK-ENCODING: [0xbc,0x2b,0x7f,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: bc 2b 7f 05 <unknown>
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tbl z28.s, { z29.s, z30.s }, z31.s
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// CHECK-INST: tbl z28.s, { z29.s, z30.s }, z31.s
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// CHECK-ENCODING: [0xbc,0x2b,0xbf,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: bc 2b bf 05 <unknown>
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tbl z28.d, { z29.d, z30.d }, z31.d
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// CHECK-INST: tbl z28.d, { z29.d, z30.d }, z31.d
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// CHECK-ENCODING: [0xbc,0x2b,0xff,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: bc 2b ff 05 <unknown>
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@ -0,0 +1,22 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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tbx z0.b, z1.b, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: tbx z0.b, z1.b, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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tbx z31.d, z31.d, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbx z31.d, z31.d, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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tbx z31.d, z31.d, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbx z31.d, z31.d, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,32 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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tbx z31.b, z31.b, z31.b
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// CHECK-INST: tbx z31.b, z31.b, z31.b
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// CHECK-ENCODING: [0xff,0x2f,0x3f,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: ff 2f 3f 05 <unknown>
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tbx z31.h, z31.h, z31.h
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// CHECK-INST: tbx z31.h, z31.h, z31.h
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// CHECK-ENCODING: [0xff,0x2f,0x7f,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: ff 2f 7f 05 <unknown>
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tbx z31.s, z31.s, z31.s
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// CHECK-INST: tbx z31.s, z31.s, z31.s
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// CHECK-ENCODING: [0xff,0x2f,0xbf,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: ff 2f bf 05 <unknown>
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tbx z31.d, z31.d, z31.d
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// CHECK-INST: tbx z31.d, z31.d, z31.d
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// CHECK-ENCODING: [0xff,0x2f,0xff,0x05]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: ff 2f ff 05 <unknown>
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