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[X86] Avoid uses of getZextValue(). NFCI. 

Use getAPIntValue() directly - this is mainly a best practice style issue to help prevent fuzz tests blowing up when a i12345 (or whatever) is generated.

Use getConstantOperandVal/getConstantOperandAPInt wrappers where possible.

llvm-svn: 371315
This commit is contained in:
Simon Pilgrim 2019-09-07 16:13:57 +00:00
parent 31c98abda3
commit 08692e5dd1
1 changed files with 19 additions and 22 deletions
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41
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -4653,7 +4653,7 @@ static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
// X < 0 -> X == 0, jump on sign. // X < 0 -> X == 0, jump on sign.
return X86::COND_S; return X86::COND_S;
} }
if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { if (SetCCOpcode == ISD::SETLT && RHSC->getAPIntValue() == 1) {
// X < 1 -> X <= 0 // X < 1 -> X <= 0
RHS = DAG.getConstant(0, DL, RHS.getValueType()); RHS = DAG.getConstant(0, DL, RHS.getValueType());
return X86::COND_LE; return X86::COND_LE;
@ -6769,7 +6769,7 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
Mask.push_back(SM_SentinelUndef); Mask.push_back(SM_SentinelUndef);
continue; continue;
} }
uint64_t ByteBits = EltBits[i].getZExtValue(); const APInt &ByteBits = EltBits[i];
if (ByteBits != 0 && ByteBits != 255) if (ByteBits != 0 && ByteBits != 255)
return false; return false;
Mask.push_back(ByteBits == ZeroMask ? SM_SentinelZero : i); Mask.push_back(ByteBits == ZeroMask ? SM_SentinelZero : i);
@ -9450,7 +9450,7 @@ LowerBUILD_VECTORAsVariablePermute(SDValue V, SelectionDAG &DAG,
return SDValue(); return SDValue();
auto *PermIdx = dyn_cast<ConstantSDNode>(ExtractedIndex.getOperand(1)); auto *PermIdx = dyn_cast<ConstantSDNode>(ExtractedIndex.getOperand(1));
if (!PermIdx || PermIdx->getZExtValue() != Idx) if (!PermIdx || PermIdx->getAPIntValue() != Idx)
return SDValue(); return SDValue();
} }
@ -21092,8 +21092,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
Cond.getOperand(1).getOpcode() == X86ISD::CMP && Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
isNullConstant(Cond.getOperand(1).getOperand(1))) { isNullConstant(Cond.getOperand(1).getOperand(1))) {
SDValue Cmp = Cond.getOperand(1); SDValue Cmp = Cond.getOperand(1);
unsigned CondCode = unsigned CondCode = Cond.getConstantOperandVal(0);
cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) && if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
(CondCode == X86::COND_E || CondCode == X86::COND_NE)) { (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
@ -22142,7 +22141,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SDNode *Node = Op.getNode(); SDNode *Node = Op.getNode();
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1); SDValue Size = Op.getOperand(1);
unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); unsigned Align = Op.getConstantOperandVal(2);
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
// Chain the dynamic stack allocation so that it doesn't modify the stack // Chain the dynamic stack allocation so that it doesn't modify the stack
@ -22680,13 +22679,13 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
// Helper to detect if the operand is CUR_DIRECTION rounding mode. // Helper to detect if the operand is CUR_DIRECTION rounding mode.
auto isRoundModeCurDirection = [](SDValue Rnd) { auto isRoundModeCurDirection = [](SDValue Rnd) {
if (auto *C = dyn_cast<ConstantSDNode>(Rnd)) if (auto *C = dyn_cast<ConstantSDNode>(Rnd))
return C->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION; return C->getAPIntValue() == X86::STATIC_ROUNDING::CUR_DIRECTION;
return false; return false;
}; };
auto isRoundModeSAE = [](SDValue Rnd) { auto isRoundModeSAE = [](SDValue Rnd) {
if (auto *C = dyn_cast<ConstantSDNode>(Rnd)) if (auto *C = dyn_cast<ConstantSDNode>(Rnd))
return C->getZExtValue() == X86::STATIC_ROUNDING::NO_EXC; return C->getAPIntValue() == X86::STATIC_ROUNDING::NO_EXC;
return false; return false;
}; };
@ -22707,7 +22706,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}; };
SDLoc dl(Op); SDLoc dl(Op);
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned IntNo = Op.getConstantOperandVal(0);
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo); const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
if (IntrData) { if (IntrData) {
@ -23122,7 +23121,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case COMI_RM: { // Comparison intrinsics with Sae case COMI_RM: { // Comparison intrinsics with Sae
SDValue LHS = Op.getOperand(1); SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2); SDValue RHS = Op.getOperand(2);
unsigned CondVal = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); unsigned CondVal = Op.getConstantOperandVal(3);
SDValue Sae = Op.getOperand(4); SDValue Sae = Op.getOperand(4);
SDValue FCmp; SDValue FCmp;
@ -23815,8 +23814,7 @@ EmitMaskedTruncSStore(bool SignedSat, SDValue Chain, const SDLoc &Dl,
static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) { SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); unsigned IntNo = Op.getConstantOperandVal(1);
const IntrinsicData *IntrData = getIntrinsicWithChain(IntNo); const IntrinsicData *IntrData = getIntrinsicWithChain(IntNo);
if (!IntrData) { if (!IntrData) {
switch (IntNo) { switch (IntNo) {
@ -23961,8 +23959,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
Scale, Chain, Subtarget); Scale, Chain, Subtarget);
} }
case PREFETCH: { case PREFETCH: {
SDValue Hint = Op.getOperand(6); const APInt &HintVal = Op.getConstantOperandAPInt(6);
unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
assert((HintVal == 2 || HintVal == 3) && assert((HintVal == 2 || HintVal == 3) &&
"Wrong prefetch hint in intrinsic: should be 2 or 3"); "Wrong prefetch hint in intrinsic: should be 2 or 3");
unsigned Opcode = (HintVal == 2 ? IntrData->Opc1 : IntrData->Opc0); unsigned Opcode = (HintVal == 2 ? IntrData->Opc1 : IntrData->Opc0);
@ -24058,7 +24055,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
if (verifyReturnAddressArgumentIsConstant(Op, DAG)) if (verifyReturnAddressArgumentIsConstant(Op, DAG))
return SDValue(); return SDValue();
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = Op.getConstantOperandVal(0);
SDLoc dl(Op); SDLoc dl(Op);
EVT PtrVT = getPointerTy(DAG.getDataLayout()); EVT PtrVT = getPointerTy(DAG.getDataLayout());
@ -24110,7 +24107,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
unsigned FrameReg = unsigned FrameReg =
RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction()); RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
SDLoc dl(Op); // FIXME probably not meaningful SDLoc dl(Op); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = Op.getConstantOperandVal(0);
assert(((FrameReg == X86::RBP && VT == MVT::i64) || assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
(FrameReg == X86::EBP && VT == MVT::i32)) && (FrameReg == X86::EBP && VT == MVT::i32)) &&
"Invalid Frame Register!"); "Invalid Frame Register!");
@ -25600,7 +25597,7 @@ static SDValue convertShiftLeftToScale(SDValue Amt, const SDLoc &dl,
} }
ConstantSDNode *ND = cast<ConstantSDNode>(Op); ConstantSDNode *ND = cast<ConstantSDNode>(Op);
APInt C(SVTBits, ND->getAPIntValue().getZExtValue()); APInt C(SVTBits, ND->getZExtValue());
uint64_t ShAmt = C.getZExtValue(); uint64_t ShAmt = C.getZExtValue();
if (ShAmt >= SVTBits) { if (ShAmt >= SVTBits) {
Elts.push_back(DAG.getUNDEF(SVT)); Elts.push_back(DAG.getUNDEF(SVT));
@ -26535,10 +26532,10 @@ static SDValue emitLockedStackOp(SelectionDAG &DAG,
static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget &Subtarget, static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) { SelectionDAG &DAG) {
SDLoc dl(Op); SDLoc dl(Op);
AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( AtomicOrdering FenceOrdering =
cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); static_cast<AtomicOrdering>(Op.getConstantOperandVal(1));
SyncScope::ID FenceSSID = static_cast<SyncScope::ID>( SyncScope::ID FenceSSID =
cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); static_cast<SyncScope::ID>(Op.getConstantOperandVal(2));
// The only fence that needs an instruction is a sequentially-consistent // The only fence that needs an instruction is a sequentially-consistent
// cross-thread fence. // cross-thread fence.
@ -28219,7 +28216,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
return; return;
} }
case ISD::INTRINSIC_W_CHAIN: { case ISD::INTRINSIC_W_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); unsigned IntNo = N->getConstantOperandVal(1);
switch (IntNo) { switch (IntNo) {
default : llvm_unreachable("Do not know how to custom type " default : llvm_unreachable("Do not know how to custom type "
"legalize this intrinsic operation!"); "legalize this intrinsic operation!");