forked from OSchip/llvm-project
[InstCombine] add tests for left-shift-of-right-shifted constant; NFC
The tests are adapted from the sibling folds' tests (see D127122).
This commit is contained in:
Sanjay Patel
parent
a4d2c5ecaa
commit
0856a6cb7a
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@ -583,3 +583,135 @@ define i16 @shl_lshr_demand6(i16 %x) {
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%r = and i16 %lshr, 4094 ; 0b0000_1111_1111_1110
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ret i16 %r
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}
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define i8 @lshr_shl_demand1(i8 %x) {
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; CHECK-LABEL: @lshr_shl_demand1(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i8 28, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 [[SHR]], 3
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; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], 7
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shr = lshr i8 28, %x ; 0b0001_1100
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%shl = shl i8 %shr, 3
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%r = or i8 %shl, 7 ; 0b0000_0111
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ret i8 %r
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}
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define i8 @lshr_shl_demand2(i8 %x) {
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; CHECK-LABEL: @lshr_shl_demand2(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i8 28, [[X:%.*]]
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; CHECK-NEXT: call void @use8(i8 [[SHR]])
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 [[SHR]], 3
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; CHECK-NEXT: [[R:%.*]] = and i8 [[SHL]], -16
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shr = lshr i8 28, %x ; 0b0001_1100
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call void @use8(i8 %shr)
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%shl = shl i8 %shr, 3
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%r = and i8 %shl, -16 ; 0b1111_0000
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ret i8 %r
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}
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define i8 @lshr_shl_demand3(i8 %x) {
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; CHECK-LABEL: @lshr_shl_demand3(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i8 28, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 [[SHR]], 3
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; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], 3
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shr = lshr i8 28, %x ; 0b0001_1100
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%shl = shl i8 %shr, 3
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%r = or i8 %shl, 3 ; 0b0000_0011
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ret i8 %r
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}
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define i8 @lshr_shl_demand4(i8 %x) {
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; CHECK-LABEL: @lshr_shl_demand4(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i8 60, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[SHR]], 3
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; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], 7
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shr = lshr i8 60, %x ; 0b0011_1100
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%shl = shl i8 %shr, 3
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%r = or i8 %shl, 7 ; 0b0000_0111
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ret i8 %r
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}
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define <2 x i8> @lshr_shl_demand5(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 45>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i8> [[SHR]], <i8 2, i8 2>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 108, i8 108>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 45, i8 45>, %x ; 0b0010_1101
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%shl = shl <2 x i8> %shr, <i8 2, i8 2>
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%r = and <2 x i8> %shl, <i8 108, i8 108> ; 0b0110_1100
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ret <2 x i8> %r
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}
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define <2 x i8> @lshr_shl_demand5_undef_left(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5_undef_left(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 45>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 undef, i8 2>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 108, i8 108>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 45, i8 45>, %x ; 0b0010_1101
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%shl = shl <2 x i8> %shr, <i8 undef, i8 2>
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%r = and <2 x i8> %shl, <i8 108, i8 108> ; 0b0110_1100
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ret <2 x i8> %r
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}
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define <2 x i8> @lshr_shl_demand5_undef_right(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5_undef_right(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 undef, i8 45>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 2, i8 2>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 108, i8 108>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 undef, i8 45>, %x ; 0b0010_1101
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%shl = shl <2 x i8> %shr, <i8 2, i8 2>
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%r = and <2 x i8> %shl, <i8 108, i8 108> ; 0b0110_1100
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ret <2 x i8> %r
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}
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define <2 x i8> @lshr_shl_demand5_nonuniform_vec_left(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5_nonuniform_vec_left(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 45>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 1, i8 2>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 108, i8 108>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 45, i8 45>, %x ; 0b0010_1101
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%shl = shl <2 x i8> %shr, <i8 1, i8 2>
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%r = and <2 x i8> %shl, <i8 108, i8 108> ; 0b0110_1100
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ret <2 x i8> %r
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}
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define <2 x i8> @lshr_shl_demand5_nonuniform_vec_right(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5_nonuniform_vec_right(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 13>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 2, i8 2>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 108, i8 108>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 45, i8 13>, %x ; 0b0010_1101. 0b0000_1101
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%shl = shl <2 x i8> %shr, <i8 2, i8 2>
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%r = and <2 x i8> %shl, <i8 108, i8 108> ; 0b0110_1100
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ret <2 x i8> %r
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}
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define <2 x i8> @lshr_shl_demand5_nonuniform_vec_both(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_shl_demand5_nonuniform_vec_both(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 13>, [[X:%.*]]
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 2, i8 4>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[SHL]], <i8 -4, i8 -16>
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%shr = lshr <2 x i8> <i8 45, i8 13>, %x ; 0b0010_1101. 0b0000_1101
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%shl = shl <2 x i8> %shr, <i8 2, i8 4>
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%r = and <2 x i8> %shl, <i8 -4, i8 -16>
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ret <2 x i8> %r
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}
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