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[SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef. 

The result of sign_extend_inreg needs to have as many sign bits
as requested by the VT argument. The easiest way to guarantee this
is to fold it to 0.

SystemZ test was modified to avoid using undef.

Fixes https://github.com/llvm/llvm-project/issues/55178

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D124696
This commit is contained in:
Craig Topper 2022-05-05 09:40:10 -07:00
parent bb0aa574e7
commit 084f967370
3 changed files with 10 additions and 8 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -6225,9 +6225,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
std::swap(N1, N2);
} else {
switch (Opcode) {
case ISD::SIGN_EXTEND_INREG:
case ISD::SUB:
return getUNDEF(VT); // fold op(undef, arg2) -> undef
case ISD::SIGN_EXTEND_INREG:
case ISD::UDIV:
case ISD::SDIV:
case ISD::UREM:

5
llvm/test/CodeGen/AArch64/pr55178.ll
View File

@ -10,8 +10,9 @@ define i1 @test14(i8 %X) {
; CHECK-NEXT: mov w8, #-113
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: lsl w8, w8, w0
; CHECK-NEXT: cmp w8, w8, sxtb
; CHECK-NEXT: cset w0, lt
; CHECK-NEXT: sxtb w8, w8
; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
%1 = shl i8 -113, %X
%cmp = icmp slt i8 undef, %1

11
llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
View File

@ -11,18 +11,19 @@
@g_151 = external dso_local global i32, align 4
@g_222 = external dso_local unnamed_addr global [7 x [10 x i8]], align 2
define void @main() {
define void @main(i16 %in) {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: lhr %r2, %r2
; CHECK-NEXT: larl %r1, g_151
; CHECK-NEXT: lghi %r3, 0
; CHECK-NEXT: chi %r0, 0
; CHECK-NEXT: chi %r2, 0
; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: locghile %r3, 1
; CHECK-NEXT: o %r0, 0(%r1)
; CHECK-NEXT: dsgfr %r2, %r0
; CHECK-NEXT: larl %r1, g_222
; CHECK-NEXT: lghi %r5, 0
; CHECK-NEXT: dsgfr %r2, %r0
; CHECK-NEXT: stgrl %r2, g_39
; CHECK-NEXT: stc %r5, 19(%r1)
; CHECK-NEXT: br %r14
@ -32,7 +33,7 @@ define void @main() {
%tmp5 = srem i64 0, %tmp4
%tmp6 = trunc i64 %tmp5 to i8
store i8 %tmp6, i8* getelementptr inbounds ([7 x [10 x i8]], [7 x [10 x i8]]* @g_222, i64 0, i64 1, i64 9), align 1
%tmp7 = icmp slt i16 undef, 1
%tmp7 = icmp slt i16 %in, 1
%tmp8 = zext i1 %tmp7 to i64
%tmp9 = srem i64 %tmp8, %tmp4
store i64 %tmp9, i64* @g_39, align 8