forked from OSchip/llvm-project
[AArch64] Keep track of MIFlags in the LoadStoreOptimizer
Merging: * $x26, $x25 = frame-setup LDPXi $sp, 0 * $sp = frame-destroy ADDXri $sp, 64, 0 into an LDPXpost should preserve the flags from both instructions as following: * frame-setup frame-destroy LDPXpost Differential Revision: https://reviews.llvm.org/D44446 llvm-svn: 327533
This commit is contained in:
Francis Visoiu Mistrih
parent
bec5df2d05
commit
084e7d8770
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@ -1317,6 +1317,11 @@ public:
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/// modify the memrefs of the this MachineInstr.
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std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
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/// Return the MIFlags which represent both MachineInstrs. This
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/// should be used when merging two MachineInstrs into one. This routine does
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/// not modify the MIFlags of this MachineInstr.
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uint8_t mergeFlagsWith(const MachineInstr& Other) const;
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/// Clear this MachineInstr's memory reference descriptor list. This resets
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/// the memrefs to their most conservative state. This should be used only
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/// as a last resort since it greatly pessimizes our knowledge of the memory
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@ -381,6 +381,12 @@ MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
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return std::make_pair(MemBegin, CombinedNumMemRefs);
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}
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uint8_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
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// For now, the just return the union of the flags. If the flags get more
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// complicated over time, we might need more logic here.
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return getFlags() | Other.getFlags();
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}
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bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
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assert(!isBundledWithPred() && "Must be called on bundle header");
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for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
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@ -702,7 +702,8 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
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.addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
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.add(BaseRegOp)
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.addImm(OffsetImm)
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.setMemRefs(I->mergeMemRefsWith(*MergeMI));
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.setMemRefs(I->mergeMemRefsWith(*MergeMI))
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.setMIFlags(I->mergeFlagsWith(*MergeMI));
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(void)MIB;
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DEBUG(dbgs() << "Creating wider store. Replacing instructions:\n ");
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@ -818,7 +819,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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.add(RegOp1)
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.add(BaseRegOp)
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.addImm(OffsetImm)
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.setMemRefs(I->mergeMemRefsWith(*Paired));
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.setMemRefs(I->mergeMemRefsWith(*Paired))
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.setMIFlags(I->mergeFlagsWith(*Paired));
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(void)MIB;
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@ -913,7 +915,8 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
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TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
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.addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
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.add(StMO)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
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.setMIFlags(LoadI->getFlags());
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} else {
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// FIXME: Currently we disable this transformation in big-endian targets as
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// performance and correctness are verified only in little-endian.
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@ -954,7 +957,8 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
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TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
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DestReg)
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.add(StMO)
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.addImm(AndMaskEncoded);
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.addImm(AndMaskEncoded)
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.setMIFlags(LoadI->getFlags());
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} else {
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BitExtMI =
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BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
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@ -962,7 +966,8 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
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DestReg)
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.add(StMO)
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.addImm(Immr)
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.addImm(Imms);
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.addImm(Imms)
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.setMIFlags(LoadI->getFlags());
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}
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}
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@ -1352,7 +1357,8 @@ AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
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.add(getLdStRegOp(*I))
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.add(getLdStBaseOp(*I))
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.addImm(Value)
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.setMemRefs(I->memoperands_begin(), I->memoperands_end());
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.setMemRefs(I->memoperands_begin(), I->memoperands_end())
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.setMIFlags(I->mergeFlagsWith(*Update));
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} else {
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// Paired instruction.
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int Scale = getMemScale(*I);
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@ -1362,7 +1368,8 @@ AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
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.add(getLdStRegOp(*I, 1))
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.add(getLdStBaseOp(*I))
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.addImm(Value / Scale)
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.setMemRefs(I->memoperands_begin(), I->memoperands_end());
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.setMemRefs(I->memoperands_begin(), I->memoperands_end())
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.setMIFlags(I->mergeFlagsWith(*Update));
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}
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(void)MIB;
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@ -0,0 +1,99 @@
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# RUN: llc -run-pass=aarch64-ldst-opt -o - -mtriple=aarch64-- %s | FileCheck %s
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# Check that we merge the MIFlags from both the instructions in the final
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# instruction.
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---
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name: case11
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# CHECK-LABEL: name: case11
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body: |
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bb.0:
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frame-setup STRWui $w1, $x0, 1 :: (store 4)
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$w1 = frame-destroy LDRWui $x0, 1 :: (load 4)
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; CHECK: frame-setup STRWui
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; CHECK-NOT: frame-setup
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; CHECK-NEXT: frame-destroy ORRWrs
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; No merging happening here, make sure we keep the flags of the previous
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; instruction.
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RET_ReallyLR
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...
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---
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name: case12
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# CHECK-LABEL: name: case12
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body: |
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bb.0:
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frame-setup STRWui $w1, $x0, 1 :: (store 4)
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$w2 = frame-destroy LDRHHui $x0, 2 :: (load 2)
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; CHECK: frame-setup STRWui
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; CHECK-NOT: frame-setup
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; CHECK-NEXT: frame-destroy ANDWri
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; No merging happening here, make sure we keep the flags of the previous
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; instruction.
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RET_ReallyLR
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...
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---
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name: case13
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# CHECK-LABEL: name: case13
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body: |
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bb.0:
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frame-setup STRWui $w1, $x0, 1 :: (store 4)
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$w2 = frame-destroy LDRHHui $x0, 3 :: (load 2)
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; CHECK: frame-setup STRWui
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; CHECK-NOT: frame-setup
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; CHECK-NEXT: frame-destroy UBFMWri
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; No merging happening here, make sure we keep the flags of the previous
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; instruction.
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RET_ReallyLR
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...
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---
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name: case2
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# CHECK-LABEL: name: case2
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body: |
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bb.0:
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frame-setup STRHHui $wzr, $x0, 0 :: (store 4)
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frame-destroy STRHHui $wzr, $x0, 1 :: (store 4)
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; CHECK: frame-setup frame-destroy STRWui
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RET_ReallyLR
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...
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---
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name: case3
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# CHECK-LABEL: name: case3
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body: |
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bb.0:
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$x0 = frame-setup LDRXui $x2, 0 :: (load 8)
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$x1 = frame-destroy LDRXui $x2, 1 :: (load 8)
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; CHECK: frame-setup frame-destroy LDPXi
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RET_ReallyLR
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...
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---
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name: case4
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# CHECK-LABEL: name: case4
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body: |
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bb.0:
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$x26, $x25 = frame-setup LDPXi $sp, 0
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$sp = frame-destroy ADDXri $sp, 64, 0
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; CHECK: = frame-setup frame-destroy LDPXpost
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RET_ReallyLR
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...
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---
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name: case41
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# CHECK-LABEL: name: case41
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body: |
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bb.0:
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$x26 = frame-setup LDRXui $sp, 0
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$sp = frame-destroy ADDXri $sp, 64, 0
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; CHECK: = frame-setup frame-destroy LDRXpost
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RET_ReallyLR
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...
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