forked from OSchip/llvm-project
[AMDGPU] Update AMDGPU PAL usage documentation
Change-Id: I65f3edcfe5063551cad5aab0da1374c3a6ccd3a2
This commit is contained in:
Tim Renouf
parent
c352a2b829
commit
083b0f1b40
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@ -10959,140 +10959,384 @@ AMDPAL
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------
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------
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This section provides code conventions used when the target triple OS is
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This section provides code conventions used when the target triple OS is
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``amdpal`` (see :ref:`amdgpu-target-triples`) for passing runtime parameters
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``amdpal`` (see :ref:`amdgpu-target-triples`).
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from the application/runtime to each invocation of a hardware shader. These
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parameters include both generic, application-controlled parameters called
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*user data* as well as system-generated parameters that are a product of the
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draw or dispatch execution.
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User Data
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.. _amdgpu-amdpal-code-object-metadata-section:
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~~~~~~~~~
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Each hardware stage has a set of 32-bit *user data registers* which can be
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Code Object Metadata
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written from a command buffer and then loaded into SGPRs when waves are launched
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~~~~~~~~~~~~~~~~~~~~
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via a subsequent dispatch or draw operation. This is the way most arguments are
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passed from the application/runtime to a hardware shader.
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Compute User Data
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~~~~~~~~~~~~~~~~~
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Compute shader user data mappings are simpler than graphics shaders and have a
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fixed mapping.
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Note that there are always 10 available *user data entries* in registers -
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entries beyond that limit must be fetched from memory (via the spill table
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pointer) by the shader.
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.. table:: PAL Compute Shader User Data Registers
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:name: pal-compute-user-data-registers
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============= ================================
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User Register Description
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============= ================================
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0 Global Internal Table (32-bit pointer)
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1 Per-Shader Internal Table (32-bit pointer)
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2 - 11 Application-Controlled User Data (10 32-bit values)
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12 Spill Table (32-bit pointer)
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13 - 14 Thread Group Count (64-bit pointer)
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15 GDS Range
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============= ================================
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Graphics User Data
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~~~~~~~~~~~~~~~~~~
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Graphics pipelines support a much more flexible user data mapping:
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.. table:: PAL Graphics Shader User Data Registers
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:name: pal-graphics-user-data-registers
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============= ================================
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User Register Description
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============= ================================
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0 Global Internal Table (32-bit pointer)
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+ Per-Shader Internal Table (32-bit pointer)
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+ 1-15 Application Controlled User Data
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(1-15 Contiguous 32-bit Values in Registers)
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+ Spill Table (32-bit pointer)
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+ Draw Index (First Stage Only)
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+ Vertex Offset (First Stage Only)
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+ Instance Offset (First Stage Only)
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============= ================================
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The placement of the global internal table remains fixed in the first *user
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data SGPR register*. Otherwise all parameters are optional, and can be mapped
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to any desired *user data SGPR register*, with the following restrictions:
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* Draw Index, Vertex Offset, and Instance Offset can only be used by the first
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active hardware stage in a graphics pipeline (i.e. where the API vertex
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shader runs).
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* Application-controlled user data must be mapped into a contiguous range of
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user data registers.
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* The application-controlled user data range supports compaction remapping, so
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only *entries* that are actually consumed by the shader must be assigned to
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corresponding *registers*. Note that in order to support an efficient runtime
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implementation, the remapping must pack *registers* in the same order as
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*entries*, with unused *entries* removed.
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.. _pal_global_internal_table:
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Global Internal Table
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~~~~~~~~~~~~~~~~~~~~~
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The global internal table is a table of *shader resource descriptors* (SRDs)
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that define how certain engine-wide, runtime-managed resources should be
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accessed from a shader. The majority of these resources have HW-defined formats,
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and it is up to the compiler to write/read data as required by the target
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hardware.
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The following table illustrates the required format:
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.. table:: PAL Global Internal Table
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:name: pal-git-table
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============= ================================
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Offset Description
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============= ================================
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0-3 Graphics Scratch SRD
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4-7 Compute Scratch SRD
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8-11 ES/GS Ring Output SRD
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12-15 ES/GS Ring Input SRD
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16-19 GS/VS Ring Output #0
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20-23 GS/VS Ring Output #1
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24-27 GS/VS Ring Output #2
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28-31 GS/VS Ring Output #3
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32-35 GS/VS Ring Input SRD
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36-39 Tessellation Factor Buffer SRD
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40-43 Off-Chip LDS Buffer SRD
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44-47 Off-Chip Param Cache Buffer SRD
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48-51 Sample Position Buffer SRD
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52 vaRange::ShadowDescriptorTable High Bits
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============= ================================
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The pointer to the global internal table passed to the shader as user data
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is a 32-bit pointer. The top 32 bits should be assumed to be the same as
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the top 32 bits of the pipeline, so the shader may use the program
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counter's top 32 bits.
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.. _pal_call-convention:
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Call Convention
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~~~~~~~~~~~~~~~
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For graphics use cases, the calling convention is `amdgpu_gfx`.
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.. note::
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.. note::
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`amdgpu_gfx` Function calls are currently in development and are
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The metadata is currently in development and is subject to major
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subject to major changes.
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changes. Only the current version is supported. *When this document
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was generated the version was 2.6.*
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This calling convention shares most properties with calling non-kernel
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Code object metadata is specified by the ``NT_AMDGPU_METADATA`` note
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functions (see
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record (see :ref:`amdgpu-note-records-v3-v4`).
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:ref:`amdgpu-amdhsa-function-call-convention-non-kernel-functions`).
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Differences are:
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- Currently there are none, differences will be listed here
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The metadata is represented as Message Pack formatted binary data (see
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[MsgPack]_). The top level is a Message Pack map that includes the keys
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defined in table :ref:`amdgpu-amdpal-code-object-metadata-map-table`
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and referenced tables.
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Additional information can be added to the maps. To avoid conflicts, any
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key names should be prefixed by "*vendor-name*." where ``vendor-name``
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can be the name of the vendor and specific vendor tool that generates the
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information. The prefix is abbreviated to simply "." when it appears
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within a map that has been added by the same *vendor-name*.
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.. table:: AMDPAL Code Object Metadata Map
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:name: amdgpu-amdpal-code-object-metadata-map-table
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=================== ============== ========= ======================================================================
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String Key Value Type Required? Description
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=================== ============== ========= ======================================================================
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"amdpal.version" sequence of Required PAL code object metadata (major, minor) version. The current values
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2 integers are defined by *Util::Abi::PipelineMetadata(Major|Minor)Version*.
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"amdpal.pipelines" sequence of Required Per-pipeline metadata. See
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map :ref:`amdgpu-amdpal-code-object-pipeline-metadata-map-table` for the
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definition of the keys included in that map.
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=================== ============== ========= ======================================================================
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..
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.. table:: AMDPAL Code Object Pipeline Metadata Map
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:name: amdgpu-amdpal-code-object-pipeline-metadata-map-table
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====================================== ============== ========= ===================================================
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String Key Value Type Required? Description
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====================================== ============== ========= ===================================================
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".name" string Source name of the pipeline.
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".type" string Pipeline type, e.g. VsPs. Values include:
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- "VsPs"
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- "Gs"
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- "Cs"
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- "Ngg"
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- "Tess"
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- "GsTess"
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- "NggTess"
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".internal_pipeline_hash" sequence of Required Internal compiler hash for this pipeline. Lower
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2 integers 64 bits is the "stable" portion of the hash, used
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for e.g. shader replacement lookup. Upper 64 bits
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is the "unique" portion of the hash, used for
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e.g. pipeline cache lookup. The value is
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implementation defined, and can not be relied on
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between different builds of the compiler.
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".shaders" map Per-API shader metadata. See
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:ref:`amdgpu-amdpal-code-object-shader-map-table`
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for the definition of the keys included in that
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map.
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".hardware_stages" map Per-hardware stage metadata. See
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:ref:`amdgpu-amdpal-code-object-hardware-stage-map-table`
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for the definition of the keys included in that
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map.
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".shader_functions" map Per-shader function metadata. See
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:ref:`amdgpu-amdpal-code-object-shader-function-map-table`
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for the definition of the keys included in that
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map.
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".registers" map Required Hardware register configuration. See
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:ref:`amdgpu-amdpal-code-object-register-map-table`
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for the definition of the keys included in that
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map.
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".user_data_limit" integer Number of user data entries accessed by this
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pipeline.
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".spill_threshold" integer The user data spill threshold. 0xFFFF for
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NoUserDataSpilling.
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".uses_viewport_array_index" boolean Indicates whether or not the pipeline uses the
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viewport array index feature. Pipelines which use
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this feature can render into all 16 viewports,
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whereas pipelines which do not use it are
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restricted to viewport #0.
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".es_gs_lds_size" integer Size in bytes of LDS space used internally for
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handling data-passing between the ES and GS
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shader stages. This can be zero if the data is
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passed using off-chip buffers. This value should
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be used to program all user-SGPRs which have been
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marked with "UserDataMapping::EsGsLdsSize"
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(typically only the GS and VS HW stages will ever
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have a user-SGPR so marked).
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".nggSubgroupSize" integer Explicit maximum subgroup size for NGG shaders
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(maximum number of threads in a subgroup).
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".num_interpolants" integer Graphics only. Number of PS interpolants.
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".mesh_scratch_memory_size" integer Max mesh shader scratch memory used.
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".api" string Name of the client graphics API.
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".api_create_info" binary Graphics API shader create info binary blob. Can
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be defined by the driver using the compiler if
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they want to be able to correlate API-specific
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information used during creation at a later time.
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====================================== ============== ========= ===================================================
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..
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.. table:: AMDPAL Code Object Shader Map
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:name: amdgpu-amdpal-code-object-shader-map-table
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+-------------+--------------+-------------------------------------------------------------------+
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|String Key |Value Type |Description |
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+=============+==============+===================================================================+
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|- ".compute" |map |See :ref:`amdgpu-amdpal-code-object-api-shader-metadata-map-table` |
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|- ".vertex" | |for the definition of the keys included in that map. |
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|- ".hull" | | |
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|- ".domain" | | |
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|- ".geometry"| | |
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|- ".pixel" | | |
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+-------------+--------------+-------------------------------------------------------------------+
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..
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.. table:: AMDPAL Code Object API Shader Metadata Map
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:name: amdgpu-amdpal-code-object-api-shader-metadata-map-table
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==================== ============== ========= =====================================================================
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String Key Value Type Required? Description
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==================== ============== ========= =====================================================================
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".api_shader_hash" sequence of Required Input shader hash, typically passed in from the client. The value
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2 integers is implementation defined, and can not be relied on between
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different builds of the compiler.
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".hardware_mapping" sequence of Required Flags indicating the HW stages this API shader maps to. Values
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string include:
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- ".ls"
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- ".hs"
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- ".es"
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- ".gs"
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- ".vs"
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- ".ps"
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- ".cs"
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==================== ============== ========= =====================================================================
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..
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.. table:: AMDPAL Code Object Hardware Stage Map
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:name: amdgpu-amdpal-code-object-hardware-stage-map-table
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+-------------+--------------+-----------------------------------------------------------------------+
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|String Key |Value Type |Description |
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+=============+==============+=======================================================================+
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|- ".ls" |map |See :ref:`amdgpu-amdpal-code-object-hardware-stage-metadata-map-table` |
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|- ".hs" | |for the definition of the keys included in that map. |
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|- ".es" | | |
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|- ".gs" | | |
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|- ".vs" | | |
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|- ".ps" | | |
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|- ".cs" | | |
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+-------------+--------------+-----------------------------------------------------------------------+
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..
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.. table:: AMDPAL Code Object Hardware Stage Metadata Map
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:name: amdgpu-amdpal-code-object-hardware-stage-metadata-map-table
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========================== ============== ========= ===============================================================
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String Key Value Type Required? Description
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========================== ============== ========= ===============================================================
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".entry_point" string The ELF symbol pointing to this pipeline's stage entry point.
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".scratch_memory_size" integer Scratch memory size in bytes.
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".lds_size" integer Local Data Share size in bytes.
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".perf_data_buffer_size" integer Performance data buffer size in bytes.
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".vgpr_count" integer Number of VGPRs used.
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".sgpr_count" integer Number of SGPRs used.
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".vgpr_limit" integer If non-zero, indicates the shader was compiled with a
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directive to instruct the compiler to limit the VGPR usage to
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be less than or equal to the specified value (only set if
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different from HW default).
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".sgpr_limit" integer SGPR count upper limit (only set if different from HW
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default).
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".threadgroup_dimensions" sequence of Thread-group X/Y/Z dimensions (Compute only).
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3 integers
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".wavefront_size" integer Wavefront size (only set if different from HW default).
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".uses_uavs" boolean The shader reads or writes UAVs.
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".uses_rovs" boolean The shader reads or writes ROVs.
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".writes_uavs" boolean The shader writes to one or more UAVs.
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".writes_depth" boolean The shader writes out a depth value.
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".uses_append_consume" boolean The shader uses append and/or consume operations, either
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memory or GDS.
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".uses_prim_id" boolean The shader uses PrimID.
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========================== ============== ========= ===============================================================
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..
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.. table:: AMDPAL Code Object Shader Function Map
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:name: amdgpu-amdpal-code-object-shader-function-map-table
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=============== ============== ====================================================================
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String Key Value Type Description
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=============== ============== ====================================================================
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*symbol name* map *symbol name* is the ELF symbol name of the shader function code
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entry address. The value is the function's metadata. See
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:ref:`amdgpu-amdpal-code-object-shader-function-metadata-map-table`.
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=============== ============== ====================================================================
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..
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.. table:: AMDPAL Code Object Shader Function Metadata Map
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:name: amdgpu-amdpal-code-object-shader-function-metadata-map-table
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============================= ============== =================================================================
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String Key Value Type Description
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============================= ============== =================================================================
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".api_shader_hash" sequence of Input shader hash, typically passed in from the client. The value
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2 integers is implementation defined, and can not be relied on between
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different builds of the compiler.
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".scratch_memory_size" sequence of Size in bytes of scratch memory used by the shader.
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2 integers
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".lds_size" sequence of Size in bytes of LDS memory.
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2 integers
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".vgpr_count" integer Number of VGPRs used by the shader.
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".sgpr_count" integer Number of SGPRs used by the shader.
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".stack_frame_size_in_bytes" integer Amount of stack size used by the shader.
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".shader_subtype" string Shader subtype/kind. Values include:
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- "Unknown"
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============================= ============== =================================================================
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..
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.. table:: AMDPAL Code Object Register Map
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:name: amdgpu-amdpal-code-object-register-map-table
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========================== ============== ====================================================================
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32-bit Integer Key Value Type Description
|
||||||
|
========================== ============== ====================================================================
|
||||||
|
``reg offset`` 32-bit integer ``reg offset`` is the dword offset into the GFXIP register space of
|
||||||
|
a GRBM register (i.e., driver accessible GPU register number, not
|
||||||
|
shader GPR register number). The driver is required to program each
|
||||||
|
specified register to the corresponding specified value when
|
||||||
|
executing this pipeline. Typically, the ``reg offsets`` are the
|
||||||
|
``uint16_t`` offsets to each register as defined by the hardware
|
||||||
|
chip headers. The register is set to the provided value. However, a
|
||||||
|
``reg offset`` that specifies a user data register (e.g.,
|
||||||
|
COMPUTE_USER_DATA_0) needs special treatment. See
|
||||||
|
:ref:`amdgpu-amdpal-code-object-user-data-section` section for more
|
||||||
|
information.
|
||||||
|
========================== ============== ====================================================================
|
||||||
|
|
||||||
|
.. _amdgpu-amdpal-code-object-user-data-section:
|
||||||
|
|
||||||
|
User Data
|
||||||
|
+++++++++
|
||||||
|
|
||||||
|
Each hardware stage has a set of 32-bit physical SPI *user data registers*
|
||||||
|
(either 16 or 32 based on graphics IP and the stage) which can be
|
||||||
|
written from a command buffer and then loaded into SGPRs when waves are
|
||||||
|
launched via a subsequent dispatch or draw operation. This is the way
|
||||||
|
most arguments are passed from the application/runtime to a hardware
|
||||||
|
shader.
|
||||||
|
|
||||||
|
PAL abstracts this functionality by exposing a set of 128 *user data
|
||||||
|
entries* per pipeline a client can use to pass arguments from a command
|
||||||
|
buffer to one or more shaders in that pipeline. The ELF code object must
|
||||||
|
specify a mapping from virtualized *user data entries* to physical *user
|
||||||
|
data registers*, and PAL is responsible for implementing that mapping,
|
||||||
|
including spilling overflow *user data entries* to memory if needed.
|
||||||
|
|
||||||
|
Since the *user data registers* are GRBM-accessible SPI registers, this
|
||||||
|
mapping is actually embedded in the ``.registers`` metadata entry. For
|
||||||
|
most registers, the value in that map is a literal 32-bit value that
|
||||||
|
should be written to the register by the driver. However, when the
|
||||||
|
register is a *user data register* (any USER_DATA register e.g.,
|
||||||
|
SPI_SHADER_USER_DATA_PS_5), the value is instead an encoding that tells
|
||||||
|
the driver to write either a *user data entry* value or one of several
|
||||||
|
driver-internal values to the register. This encoding is described in
|
||||||
|
the following table:
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
|
||||||
|
Currently, *user data registers* 0 and 1 (e.g., SPI_SHADER_USER_DATA_PS_0,
|
||||||
|
and SPI_SHADER_USER_DATA_PS_1) are reserved. *User data register* 0 must
|
||||||
|
always be programmed to the address of the GlobalTable, and *user data
|
||||||
|
register* 1 must always be programmed to the address of the PerShaderTable.
|
||||||
|
|
||||||
|
..
|
||||||
|
|
||||||
|
.. table:: AMDPAL User Data Mapping
|
||||||
|
:name: amdgpu-amdpal-code-object-metadata-user-data-mapping-table
|
||||||
|
|
||||||
|
========== ================= ===============================================================================
|
||||||
|
Value Name Description
|
||||||
|
========== ================= ===============================================================================
|
||||||
|
0..127 *User Data Entry* 32-bit value of user_data_entry[N] as specified via *CmdSetUserData()*
|
||||||
|
0x10000000 GlobalTable 32-bit pointer to GPU memory containing the global internal table (should
|
||||||
|
always point to *user data register* 0).
|
||||||
|
0x10000001 PerShaderTable 32-bit pointer to GPU memory containing the per-shader internal table. See
|
||||||
|
:ref:`amdgpu-amdpal-code-object-metadata-user-data-per-shader-table-section`
|
||||||
|
for more detail (should always point to *user data register* 1).
|
||||||
|
0x10000002 SpillTable 32-bit pointer to GPU memory containing the user data spill table. See
|
||||||
|
:ref:`amdgpu-amdpal-code-object-metadata-user-data-spill-table-section` for
|
||||||
|
more detail.
|
||||||
|
0x10000003 BaseVertex Vertex offset (32-bit unsigned integer). Not needed if the pipeline doesn't
|
||||||
|
reference the draw index in the vertex shader. Only supported by the first
|
||||||
|
stage in a graphics pipeline.
|
||||||
|
0x10000004 BaseInstance Instance offset (32-bit unsigned integer). Only supported by the first stage in
|
||||||
|
a graphics pipeline.
|
||||||
|
0x10000005 DrawIndex Draw index (32-bit unsigned integer). Only supported by the first stage in a
|
||||||
|
graphics pipeline.
|
||||||
|
0x10000006 Workgroup Thread group count (32-bit unsigned integer). Low half of a 64-bit address of
|
||||||
|
a buffer containing the grid dimensions for a Compute dispatch operation. The
|
||||||
|
high half of the address is stored in the next sequential user-SGPR. Only
|
||||||
|
supported by compute pipelines.
|
||||||
|
0x1000000A EsGsLdsSize Indicates that PAL will program this user-SGPR to contain the amount of LDS
|
||||||
|
space used for the ES/GS pseudo-ring-buffer for passing data between shader
|
||||||
|
stages.
|
||||||
|
0x1000000B ViewId View id (32-bit unsigned integer) identifies a view of graphic
|
||||||
|
pipeline instancing.
|
||||||
|
0x1000000C StreamOutTable 32-bit pointer to GPU memory containing the stream out target SRD table. This
|
||||||
|
can only appear for one shader stage per pipeline.
|
||||||
|
0x1000000D PerShaderPerfData 32-bit pointer to GPU memory containing the per-shader performance data buffer.
|
||||||
|
0x1000000F VertexBufferTable 32-bit pointer to GPU memory containing the vertex buffer SRD table. This can
|
||||||
|
only appear for one shader stage per pipeline.
|
||||||
|
0x10000010 UavExportTable 32-bit pointer to GPU memory containing the UAV export SRD table. This can
|
||||||
|
only appear for one shader stage per pipeline (PS). These replace color targets
|
||||||
|
and are completely separate from any UAVs used by the shader. This is optional,
|
||||||
|
and only used by the PS when UAV exports are used to replace color-target
|
||||||
|
exports to optimize specific shaders.
|
||||||
|
0x10000011 NggCullingData 64-bit pointer to GPU memory containing the hardware register data needed by
|
||||||
|
some NGG pipelines to perform culling. This value contains the address of the
|
||||||
|
first of two consecutive registers which provide the full GPU address.
|
||||||
|
0x10000015 FetchShaderPtr 64-bit pointer to GPU memory containing the fetch shader subroutine.
|
||||||
|
========== ================= ===============================================================================
|
||||||
|
|
||||||
|
.. _amdgpu-amdpal-code-object-metadata-user-data-per-shader-table-section:
|
||||||
|
|
||||||
|
Per-Shader Table
|
||||||
|
################
|
||||||
|
|
||||||
|
Low 32 bits of the GPU address for an optional buffer in the ``.data``
|
||||||
|
section of the ELF. The high 32 bits of the address match the high 32 bits
|
||||||
|
of the shader's program counter.
|
||||||
|
|
||||||
|
The buffer can be anything the shader compiler needs it for, and
|
||||||
|
allows each shader to have its own region of the ``.data`` section.
|
||||||
|
Typically, this could be a table of buffer SRD's and the data pointed to
|
||||||
|
by the buffer SRD's, but it could be a flat-address region of memory as
|
||||||
|
well. Its layout and usage are defined by the shader compiler.
|
||||||
|
|
||||||
|
Each shader's table in the ``.data`` section is referenced by the symbol
|
||||||
|
``_amdgpu_``\ *xs*\ ``_shdr_intrl_data`` where *xs* corresponds with the
|
||||||
|
hardware shader stage the data is for. E.g.,
|
||||||
|
``_amdgpu_cs_shdr_intrl_data`` for the compute shader hardware stage.
|
||||||
|
|
||||||
|
.. _amdgpu-amdpal-code-object-metadata-user-data-spill-table-section:
|
||||||
|
|
||||||
|
Spill Table
|
||||||
|
###########
|
||||||
|
|
||||||
|
It is possible for a hardware shader to need access to more *user data
|
||||||
|
entries* than there are slots available in user data registers for one
|
||||||
|
or more hardware shader stages. In that case, the PAL runtime expects
|
||||||
|
the necessary *user data entries* to be spilled to GPU memory and use
|
||||||
|
one user data register to point to the spilled user data memory. The
|
||||||
|
value of the *user data entry* must then represent the location where
|
||||||
|
a shader expects to read the low 32-bits of the table's GPU virtual
|
||||||
|
address. The *spill table* itself represents a set of 32-bit values
|
||||||
|
managed by the PAL runtime in GPU-accessible memory that can be made
|
||||||
|
indirectly accessible to a hardware shader.
|
||||||
|
|
||||||
Unspecified OS
|
Unspecified OS
|
||||||
--------------
|
--------------
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue