forked from OSchip/llvm-project
Improve the generated code by getCopyFromPartsVector for promoted integer types.
Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). llvm-svn: 132892
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@ -286,22 +286,10 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
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assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
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"Cannot handle this kind of promotion");
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// Promoted vector extract
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unsigned NumElts = ValueVT.getVectorNumElements();
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SmallVector<SDValue, 8> NewOps;
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
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PartVT.getScalarType(), Val ,DAG.getIntPtrConstant(i));
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SDValue Cast;
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bool Smaller = ValueVT.bitsLE(PartVT);
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return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
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DL, ValueVT, Val);
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bool Smaller = ValueVT.bitsLE(PartVT);
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Cast = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
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DL, ValueVT.getScalarType(), Ext);
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NewOps.push_back(Cast);
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}
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return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT,
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&NewOps[0], NewOps.size());
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}
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// Trivial bitcast if the types are the same size and the destination
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@ -310,9 +298,17 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
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TLI.isTypeLegal(ValueVT))
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return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
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assert(ValueVT.getVectorElementType() == PartVT &&
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ValueVT.getVectorNumElements() == 1 &&
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// Handle cases such as i8 -> <1 x i1>
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assert(ValueVT.getVectorNumElements() == 1 &&
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"Only trivial scalar-to-vector conversions should get here!");
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if (ValueVT.getVectorNumElements() == 1 &&
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ValueVT.getVectorElementType() != PartVT) {
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bool Smaller = ValueVT.bitsLE(PartVT);
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Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
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DL, ValueVT.getScalarType(), Val);
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}
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return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
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}
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@ -453,7 +449,7 @@ static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
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// Bitconvert vector->vector case.
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Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
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} else if (PartVT.isVector() &&
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PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
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PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
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PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
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EVT ElementVT = PartVT.getVectorElementType();
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// Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
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@ -475,7 +471,7 @@ static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
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//Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
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} else if (PartVT.isVector() &&
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PartVT.getVectorElementType().bitsGE(
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ValueVT.getVectorElementType())&&
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ValueVT.getVectorElementType()) &&
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PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
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// Promoted vector extract
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@ -492,11 +488,14 @@ static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
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&NewOps[0], NewOps.size());
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} else{
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// Vector -> scalar conversion.
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assert(ValueVT.getVectorElementType() == PartVT &&
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ValueVT.getVectorNumElements() == 1 &&
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assert(ValueVT.getVectorNumElements() == 1 &&
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"Only trivial vector-to-scalar conversions should get here!");
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Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
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PartVT, Val, DAG.getIntPtrConstant(0));
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bool Smaller = ValueVT.bitsLE(PartVT);
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Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
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DL, PartVT, Val);
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}
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Parts[0] = Val;
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