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[LegalizeTypes][VP] Add integer promotion support for vp.fptosi/vp.fptoui 

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125760
This commit is contained in:
Ping Deng 2022-05-30 02:52:40 +00:00 committed by Ben Shi
parent 42c3c70a9e
commit 083798e270
7 changed files with 113 additions and 3 deletions

20
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -135,6 +135,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
case ISD::VP_FPTOSI:
case ISD::VP_FPTOUI:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
@ -669,6 +671,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
NewOpc = ISD::STRICT_FP_TO_SINT;
if (N->getOpcode() == ISD::VP_FPTOUI &&
!TLI.isOperationLegal(ISD::VP_FPTOUI, NVT) &&
TLI.isOperationLegalOrCustom(ISD::VP_FPTOSI, NVT))
NewOpc = ISD::VP_FPTOSI;
SDValue Res;
if (N->isStrictFPOpcode()) {
Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
@ -676,8 +683,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
} else
} else if (NewOpc == ISD::VP_FPTOSI || NewOpc == ISD::VP_FPTOUI) {
Res = DAG.getNode(NewOpc, dl, NVT, {N->getOperand(0), N->getOperand(1),
N->getOperand(2)});
} else {
Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
}
// Assert that the converted value fits in the original type. If it doesn't
// (eg: because the value being converted is too big), then the result of the
@ -687,8 +698,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
// before legalization: fp-to-uint16, 65534. -> 0xfffe
// after legalization: fp-to-sint32, 65534. -> 0x0000fffe
return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
N->getOpcode() == ISD::STRICT_FP_TO_UINT ||
N->getOpcode() == ISD::VP_FPTOUI)
? ISD::AssertZext
: ISD::AssertSext,
dl, NVT, Res,
DAG.getValueType(N->getValueType(0).getScalarType()));
}

22
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
View File

@ -44,6 +44,28 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) {
ret <2 x i1> %z
}
define <2 x i15> @fp2si_v2f32_v2i15(<2 x float> %x) {
; CHECK-LABEL: fp2si_v2f32_v2i15:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%z = fptosi <2 x float> %x to <2 x i15>
ret <2 x i15> %z
}
define <2 x i15> @fp2ui_v2f32_v2i15(<2 x float> %x) {
; CHECK-LABEL: fp2ui_v2f32_v2i15:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%z = fptoui <2 x float> %x to <2 x i15>
ret <2 x i15> %z
}
define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
; CHECK-LABEL: fp2ui_v2f32_v2i1:
; CHECK: # %bb.0:

13
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
View File

@ -4,6 +4,19 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
declare <4 x i7> @llvm.vp.fptosi.v4i7.v4f16(<4 x half>, <4 x i1>, i32)
define <4 x i7> @vfptosi_v4i7_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i7_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <4 x i7> @llvm.vp.fptosi.v4i7.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x i7> %v
}
declare <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half>, <4 x i1>, i32)
define <4 x i8> @vfptosi_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {

13
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
View File

@ -4,6 +4,19 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh \
; RUN: -riscv-v-vector-bits-min=128 < %s | FileCheck %s
declare <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half>, <4 x i1>, i32)
define <4 x i7> @vfptoui_v4i7_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_v4i7_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x i7> %v
}
declare <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half>, <4 x i1>, i32)
define <4 x i8> @vfptoui_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {

22
llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
View File

@ -16,6 +16,28 @@ define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
ret <vscale x 1 x i1> %evec
}
define <vscale x 1 x i7> @vfptosi_nxv1f16_nxv1i7(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptosi_nxv1f16_nxv1i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i7>
ret <vscale x 1 x i7> %evec
}
define <vscale x 1 x i7> @vfptoui_nxv1f16_nxv1i7(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i7>
ret <vscale x 1 x i7> %evec
}
define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i1:
; CHECK: # %bb.0:

13
llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
View File

@ -2,6 +2,19 @@
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
declare <vscale x 2 x i7> @llvm.vp.fptosi.v4i7.v4f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i7> @vfptosi_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i7_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i7> @llvm.vp.fptosi.v4i7.v4f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i7> %v
}
declare <vscale x 2 x i8> @llvm.vp.fptosi.nxv2i8.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {

13
llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
View File

@ -2,6 +2,19 @@
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
declare <vscale x 2 x i7> @llvm.vp.fptoui.v4i7.v4f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i7> @vfptoui_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_v4i7_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i7> @llvm.vp.fptoui.v4i7.v4f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i7> %v
}
declare <vscale x 2 x i8> @llvm.vp.fptoui.nxv2i8.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @vfptoui_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {