forked from OSchip/llvm-project
StructurizeCFG: Simplify inserted PHI nodes
Summary: This improves subsequent divergence analysis in some cases. Change-Id: I5e95e7ec7fd3fa80d414d1a53a02fea23e3d67d3 Reviewers: arsenm, rampitec Subscribers: jvesely, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D53316 llvm-svn: 344697
This commit is contained in:
Nicolai Haehnle
parent
c4a2ff0950
commit
0823050b9f
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@ -13,6 +13,7 @@
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/InstructionSimplify.h"
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#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/RegionInfo.h"
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@ -596,7 +597,8 @@ void StructurizeCFG::addPhiValues(BasicBlock *From, BasicBlock *To) {
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/// Add the real PHI value as soon as everything is set up
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void StructurizeCFG::setPhiValues() {
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SSAUpdater Updater;
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SmallVector<PHINode *, 8> InsertedPhis;
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SSAUpdater Updater(&InsertedPhis);
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for (const auto &AddedPhi : AddedPhis) {
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BasicBlock *To = AddedPhi.first;
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const BBVector &From = AddedPhi.second;
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@ -632,6 +634,26 @@ void StructurizeCFG::setPhiValues() {
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DeletedPhis.erase(To);
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}
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assert(DeletedPhis.empty());
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// Simplify any phis inserted by the SSAUpdater if possible
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bool Changed;
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do {
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Changed = false;
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SimplifyQuery Q(Func->getParent()->getDataLayout());
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Q.DT = DT;
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for (size_t i = 0; i < InsertedPhis.size(); ++i) {
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PHINode *Phi = InsertedPhis[i];
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if (Value *V = SimplifyInstruction(Phi, Q)) {
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Phi->replaceAllUsesWith(V);
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Phi->eraseFromParent();
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InsertedPhis[i] = InsertedPhis.back();
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InsertedPhis.pop_back();
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i--;
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Changed = true;
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}
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}
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} while (Changed);
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}
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/// Remove phi values from all successors and then remove the terminator.
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@ -312,13 +312,12 @@ exit1: ; preds = %LeafBlock, %LeafBlock1
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; IR-LABEL: @multi_divergent_region_exit_ret_ret_return_value(
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; IR: Flow2:
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; IR: %11 = phi float [ 2.000000e+00, %exit1 ], [ undef, %Flow1 ]
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; IR: %12 = phi i1 [ false, %exit1 ], [ %16, %Flow1 ]
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; IR: call void @llvm.amdgcn.end.cf(i64 %20)
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; IR: %11 = phi i1 [ false, %exit1 ], [ %15, %Flow1 ]
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; IR: call void @llvm.amdgcn.end.cf(i64 %19)
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; IR: UnifiedReturnBlock:
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; IR: %UnifiedRetVal = phi float [ %11, %Flow2 ], [ 1.000000e+00, %exit0 ]
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; IR: call void @llvm.amdgcn.end.cf(i64 %15)
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; IR: %UnifiedRetVal = phi float [ 2.000000e+00, %Flow2 ], [ 1.000000e+00, %exit0 ]
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; IR: call void @llvm.amdgcn.end.cf(i64 %14)
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; IR: ret float %UnifiedRetVal
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define amdgpu_ps float @multi_divergent_region_exit_ret_ret_return_value(i32 %vgpr) #0 {
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entry:
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@ -353,8 +352,8 @@ exit1: ; preds = %LeafBlock, %LeafBlock1
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; GCN: {{^}}[[FLOW]]:
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; GCN: s_cbranch_vccnz [[FLOW1:BB[0-9]+]]
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; GCN: v_mov_b32_e32 v0, 2.0
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; GCN: s_or_b64 exec, exec
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; GCN: v_mov_b32_e32 v0, 2.0
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; GCN-NOT: s_and_b64 exec, exec
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; GCN: v_mov_b32_e32 v0, 1.0
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@ -33,6 +33,8 @@
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; GCN-NEXT: s_mov_b64
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; GCN-NEXT: s_and_b64 [[MASKED_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
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; GCN-NEXT: s_or_b64 [[OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED_SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
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; TODO: get rid of redundant loop counter moves
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; GCN-NEXT: v_mov_b32_e32
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; GCN-NEXT: s_andn2_b64 exec, exec, [[OR_BREAK]]
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; GCN-NEXT: s_cbranch_execnz [[INNER_LOOP]]
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@ -43,6 +45,7 @@
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; GCN-NEXT: s_or_b64 exec, exec, [[OR_BREAK]]
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; GCN-NEXT: s_and_b64 [[MASKED2_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
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; GCN-NEXT: s_or_b64 [[OUTER_OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED2_SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
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; GCN-NEXT: v_mov_b32_e32
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; GCN-NEXT: s_andn2_b64 exec, exec, [[OUTER_OR_BREAK]]
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; GCN-NEXT: s_cbranch_execnz [[OUTER_LOOP]]
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define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
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@ -592,11 +592,12 @@ exit:
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; GCN-LABEL: {{^}}smrd_uniform_loop2:
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; (this test differs from smrd_uniform_loop by the more complex structure of phis,
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; which currently confuses the DivergenceAnalysis after structurization)
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; which used to confuse the DivergenceAnalysis after structurization)
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;
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; TODO: this should use an s_buffer_load
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; TODO: we should keep the loop counter in an SGPR
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;
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; GCN: buffer_load_dword
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; GCN: v_readfirstlane_b32
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; GCN: s_buffer_load_dword
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define amdgpu_ps float @smrd_uniform_loop2(<4 x i32> inreg %desc, i32 %bound, i32 %bound.a) #0 {
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main_body:
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br label %loop
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@ -12,13 +12,12 @@ define void @invert_constantexpr_condition(i32 %arg, i32 %arg1) #0 {
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; CHECK: bb2:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP1:%.*]], [[FLOW]] ], [ [[TMP7:%.*]], [[BB6:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ undef, [[FLOW]] ], [ [[TMP7:%.*]], [[BB6:%.*]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], icmp eq (i32 ptrtoint (i32* @g to i32), i32 0)
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; CHECK-NEXT: br label [[BB8:%.*]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP1]] = phi i1 [ undef, [[BB2]] ], [ undef, [[BB:%.*]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ [[TMP0]], [[BB2]] ], [ icmp ne (i32 ptrtoint (i32* @g to i32), i32 0), [[BB]] ]
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; CHECK-NEXT: br i1 [[TMP2]], label [[BB6]], label [[BB3:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP0]], [[BB2]] ], [ icmp ne (i32 ptrtoint (i32* @g to i32), i32 0), [[BB:%.*]] ]
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; CHECK-NEXT: br i1 [[TMP1]], label [[BB6]], label [[BB3:%.*]]
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; CHECK: bb6:
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; CHECK-NEXT: [[TMP7]] = icmp slt i32 [[ARG]], [[ARG1:%.*]]
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; CHECK-NEXT: br label [[BB3]]
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@ -1,28 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -o - -structurizecfg < %s | FileCheck %s
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;
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; TODO: eliminate redundant phis for the loop counter
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;
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define void @test1() {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[CTR_NEXT:%.*]], [[LOOP_B:%.*]] ], [ [[CTR_NEXT]], [[LOOP_A:%.*]] ]
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; CHECK-NEXT: br label [[FLOW1:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[CTR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[FLOW1]] ]
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; CHECK-NEXT: [[CTR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[CTR_NEXT:%.*]], [[FLOW1]] ]
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; CHECK-NEXT: [[CTR_NEXT]] = add i32 [[CTR]], 1
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; CHECK-NEXT: br i1 undef, label [[LOOP_A]], label [[FLOW1]]
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; CHECK-NEXT: br i1 undef, label [[LOOP_A:%.*]], label [[FLOW1]]
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; CHECK: loop.a:
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; CHECK-NEXT: br i1 undef, label [[LOOP_B]], label [[FLOW:%.*]]
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; CHECK-NEXT: br i1 undef, label [[LOOP_B:%.*]], label [[FLOW:%.*]]
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; CHECK: loop.b:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP1]] = phi i32 [ [[TMP0]], [[FLOW]] ], [ undef, [[LOOP]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[FLOW]] ], [ true, [[LOOP]] ]
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; CHECK-NEXT: br i1 [[TMP2]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ false, [[FLOW]] ], [ true, [[LOOP]] ]
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; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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@ -8,33 +8,36 @@ bb:
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br label %bb3
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; CHECK: bb3:
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; CHECK: %0 = xor i1 %tmp4, true
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; CHECK: br i1 %0, label %bb5, label %Flow
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bb3: ; preds = %bb7, %bb
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%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
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%tmp4 = fcmp ult float %arg1, 3.500000e+00
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; CHECK: %0 = xor i1 %tmp4, true
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; CHECK: br i1 %0, label %bb5, label %Flow
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br i1 %tmp4, label %bb7, label %bb5
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; CHECK: bb5:
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; CHECK: %1 = xor i1 %tmp6, true
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; CHECK: br label %Flow
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bb5: ; preds = %bb3
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%tmp6 = fcmp olt float 0.000000e+00, %arg2
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; CHECK: br label %Flow
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br i1 %tmp6, label %bb10, label %bb7
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; CHECK: Flow:
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; CHECK: br i1 %3, label %bb7, label %Flow1
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; CHECK: %2 = phi i1 [ %1, %bb5 ], [ %tmp4, %bb3 ]
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; CHECK: br i1 %2, label %bb7, label %Flow1
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; CHECK: bb7
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; CHECK: bb7:
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; CHECK: br label %Flow1
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bb7: ; preds = %bb5, %bb3
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%tmp8 = add nuw nsw i64 %tmp, 1
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%tmp9 = icmp slt i64 %tmp8, 5
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; CHECK: br label %Flow1
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br i1 %tmp9, label %bb3, label %bb10
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; CHECK: Flow1:
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; CHECK: br i1 %7, label %bb10, label %bb3
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; CHECK: %6 = phi i1 [ %3, %bb7 ], [ true, %Flow ]
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; CHECK: br i1 %6, label %bb10, label %bb3
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; CHECK: bb10
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; CHECK: bb10:
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bb10: ; preds = %bb7, %bb5
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%tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
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store i32 %tmp11, i32 addrspace(1)* %arg, align 4
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