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[SystemZ] Fix register modelling in expandLoadStackGuard() 

EXPENSIVE_CHECKS found this bug (https://bugs.llvm.org/show_bug.cgi?id=33047), which
this patch fixes. The EAR instruction defines a GR32, not a GR64.

Review: Ulrich Weigand
llvm-svn: 303743
This commit is contained in:
Jonas Paulsson 2017-05-24 13:15:48 +00:00
parent 65e7206799
commit 081b5a1e9d
1 changed files with 14 additions and 16 deletions
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30
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -236,32 +236,30 @@ void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const unsigned Reg = MI->getOperand(0).getReg();
const unsigned Reg64 = MI->getOperand(0).getReg();
const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
// Conveniently, all 4 instructions are cloned from LOAD_STACK_GUARD,
// so they already have operand 0 set to reg.
// EAR can only load the low subregister so us a shift for %a0 to produce
// the GR containing %a0 and %a1.
// ear <reg>, %a0
MachineInstr *Ear1MI = MF.CloneMachineInstr(MI);
MBB->insert(MI, Ear1MI);
Ear1MI->setDesc(get(SystemZ::EAR));
MachineInstrBuilder(MF, Ear1MI).addReg(SystemZ::A0);
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
.addReg(SystemZ::A0)
.addReg(Reg64, RegState::ImplicitDefine);
// sllg <reg>, <reg>, 32
MachineInstr *SllgMI = MF.CloneMachineInstr(MI);
MBB->insert(MI, SllgMI);
SllgMI->setDesc(get(SystemZ::SLLG));
MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32);
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
.addReg(Reg64)
.addReg(0)
.addImm(32);
// ear <reg>, %a1
MachineInstr *Ear2MI = MF.CloneMachineInstr(MI);
MBB->insert(MI, Ear2MI);
Ear2MI->setDesc(get(SystemZ::EAR));
MachineInstrBuilder(MF, Ear2MI).addReg(SystemZ::A1);
BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
.addReg(SystemZ::A1);
// lg <reg>, 40(<reg>)
MI->setDesc(get(SystemZ::LG));
MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0);
MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
}
// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR