forked from OSchip/llvm-project
Remove testcases that never could have worked anyway (they print out pointer values)
llvm-svn: 5415
This commit is contained in:
Chris Lattner
parent
d090dbbeb2
commit
07f6e9fc4d
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@ -1,18 +0,0 @@
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# test/Regression/Assembler/Makefile
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#
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# This directory contains regression tests for the LLVM assembler program.
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# These LLVM source file tests are just required to assembler properly to pass.
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#
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LEVEL = ../../..
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include $(LEVEL)/test/Makefile.tests
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TESTS := $(wildcard *.ll)
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all:: $(addprefix Output/, $(TESTS:%.ll=%.out))
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Output/%.out: %.ll $(LLC) Output/.dir
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@echo "======== Testing live variables for $<"
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$(LAS) < $< | $(LLC) -f -dlivevar i -o /dev/null 1> $@ 2>&1
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diff $@ . > /dev/null 2>& 1 || \
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( rm -f $@; $(FAILURE) $@ )
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@ -1,32 +0,0 @@
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implementation
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;; Test live variable analysis:
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;; -- a simple nested loop
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;; -- a function call with arguments and return value
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int "LoopTest"(int %i, int %j)
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begin
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Start:
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%j1 = add int 0, 0
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br label %L1Header
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L1Header:
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%j2 = phi int [%j1, %Start], [%j3, %L2Done]
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%i1 = add int 0, 0 ; %i1 = 0
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br label %L2Body
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L2Body:
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%wl = phi int [%j, %L1Header], [%wl, %L2Body] ;; Useless PHI
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%i2 = phi int [%i1, %L1Header], [%i3, %L2Body]
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%i3 = add int %i2, 1
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%L2Done = seteq int %i3, 10
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br bool %L2Done, label %L2Done, label %L2Body
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L2Done:
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%j3 = add int %j2, %i3
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%L1Done = seteq int %j3, 100
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br bool %L1Done, label %L1Done, label %L1Header
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L1Done:
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%recurse = call int %LoopTest(int %j3, int %j3)
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ret int %recurse
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end
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@ -1,202 +0,0 @@
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Analysing live variables ...
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For BB 0x4c6560(L1Done) :
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Defs: 0x4c65a8(recurse) 0x726cf8
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In: 0x4c6438(j3)
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Out:
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For BB 0x4c63f0(L2Done) :
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Defs: 0x4c6438(j3) 0x4d8120 0x4ddf98 0x727280(PhiCp:)
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In: 0x4d6478(i3) 0x5ab290(j2)
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Out:
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For BB 0x5ab450(L2Body) :
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Defs: 0x4d6398(i2) 0x4d6478(i3) 0x5ab498(wl) 0x726f20 0x726ff8 0x7271c0
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In: 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out:
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For BB 0x4d82a0(L1Header) :
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Defs: 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 0x727490(PhiCp:)
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out:
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For BB 0x501700(Start) :
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Defs: 0x501748(j1) 0x727280(PhiCp:)
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In:
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Out:
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After Backward Pass 0...
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For BB L1Done:
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In: 0x4c6438(j3)
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Out:
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For BB L2Done:
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In: 0x4d6478(i3) 0x5ab290(j2)
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Out: 0x4c6438(j3)
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For BB L2Body:
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In: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out: 0x4d6478(i3) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB L1Header:
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB Start:
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In: 0x5414e0(j)
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Out: 0x5414e0(j) 0x727280(PhiCp:)
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After Backward Pass 1...
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For BB L1Done:
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In: 0x4c6438(j3)
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Out:
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For BB L2Done:
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In: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
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Out: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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For BB L2Body:
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In: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Out: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB L1Header:
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In: 0x5414e0(j) 0x727280(PhiCp:)
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Out: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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For BB Start:
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In: 0x5414e0(j)
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Out: 0x5414e0(j) 0x727280(PhiCp:)
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Live Variable Analysis complete!
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======For BB Start: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(val j1) %reg(23) %reg(val PhiCp:)*
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Before: 0x501748(j1) 0x5414e0(j)
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After : 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(23) %reg(23) %reg(val j1)*
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Before: 0x5414e0(j)
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After : 0x501748(j1) 0x5414e0(j)
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======For BB L1Header: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val j) %reg(23) %reg(val PhiCp:)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
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After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:)
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Live var sets before/after instruction add %reg(23) %reg(23) %reg(val i1)*
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Before: 0x5414e0(j) 0x5ab290(j2)
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After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1)
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val j2)*
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Before: 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x5414e0(j) 0x5ab290(j2)
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======For BB L2Body: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body)
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction nop
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction be %ccreg(val 0x726ff8) %disp(label L2Done)
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val i3) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:)
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Live var sets before/after instruction add %reg(val wl) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:)
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Live var sets before/after instruction subcc %reg(val i3) %reg(val 0x7271c0) %reg(23)* %ccreg(val 0x726ff8)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8
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Live var sets before/after instruction setsw 10 %reg(val 0x7271c0)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0
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Live var sets before/after instruction add %reg(val i2) %reg(val 0x726f20) %reg(val i3)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
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After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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Live var sets before/after instruction setsw 1 %reg(val 0x726f20)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val wl)*
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Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl)
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
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Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:)
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After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:)
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======For BB L2Done: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction nop
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Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction be %ccreg(val 0x4ddf98) %disp(label L1Done)
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Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
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After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction add %reg(val j3) %reg(23) %reg(val PhiCp:)*
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Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
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After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:)
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Live var sets before/after instruction subcc %reg(val j3) %reg(val 0x4d8120) %reg(23)* %ccreg(val 0x4ddf98)*
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Before: 0x4c6438(j3) 0x4d8120 0x5414e0(j)
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After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j)
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Live var sets before/after instruction setsw 100 %reg(val 0x4d8120)*
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Before: 0x4c6438(j3) 0x5414e0(j)
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After : 0x4c6438(j3) 0x4d8120 0x5414e0(j)
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Live var sets before/after instruction add %reg(val j2) %reg(val i3) %reg(val j3)*
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Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2)
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After : 0x4c6438(j3) 0x5414e0(j)
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======For BB L1Done: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before:
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After :
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Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4c65a8
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Before: 0x4c65a8(recurse)
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After :
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Live var sets before/after instruction nop
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Before: 0x4c65a8(recurse)
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After : 0x4c65a8(recurse)
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Live var sets before/after instruction call %disp(label LoopTest) Implicit:0x4c6438 0x4c6438 0x4c65a8* 0x726cf8*
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Before: 0x4c6438(j3)
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After : 0x4c65a8(recurse)
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@ -1,30 +0,0 @@
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implementation
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;; Test live variable analysis:
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;; -- phi argument is also used as first class value
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int "PhiTest"(int %i, int %j)
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begin
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Start:
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%i1 = add int %i, %j
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br label %L1Header
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L1Header:
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%i2 = phi int [%i1, %Start], [%i4, %L1Header]
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%i3 = add int %i1, 0
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%i4 = add int %i2, %i3
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%L1Done = setgt int %i4, 10
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br bool %L1Done, label %L1Done, label %L1Header
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L1Done:
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ret int %i4
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end
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int "main"()
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begin
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bb0:
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%result = call int %PhiTest( int 9, int 17 )
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ret int %result
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end
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@ -1,143 +0,0 @@
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Analysing live variables ...
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For BB 0x4d6510(L1Done) :
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Defs:
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In: 0x4d6398(i4)
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Out:
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For BB 0x5ab408(L1Header) :
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Defs: 0x4c6528 0x4d6350(i3) 0x4d6398(i4) 0x4ddf50 0x5ab450(i2)
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out:
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For BB 0x4d8248(Start) :
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Defs: 0x4d8290(i1) 0x726c68(PhiCp:)
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In: 0x4e4690(j) 0x501658(i)
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Out:
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After Backward Pass 0...
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For BB L1Done:
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In: 0x4d6398(i4)
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Out:
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For BB L1Header:
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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For BB Start:
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In: 0x4e4690(j) 0x501658(i)
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Out: 0x4d8290(i1) 0x726c68(PhiCp:)
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After Backward Pass 1...
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For BB L1Done:
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In: 0x4d6398(i4)
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Out:
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For BB L1Header:
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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For BB Start:
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In: 0x4e4690(j) 0x501658(i)
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Out: 0x4d8290(i1) 0x726c68(PhiCp:)
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Live Variable Analysis complete!
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======For BB Start: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d8290(i1)
|
||||
After : 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction add %reg(val i) %reg(val j) %reg(val i1)*
|
||||
Before: 0x4e4690(j) 0x501658(i)
|
||||
After : 0x4d8290(i1)
|
||||
|
||||
======For BB L1Header: Live var sets for instructions======
|
||||
|
||||
Live var sets before/after instruction nop
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction nop
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction bg %ccreg(val 0x4ddf50) %disp(label L1Done)
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction add %reg(val i4) %reg(23) %reg(val PhiCp:)*
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
|
||||
|
||||
Live var sets before/after instruction subcc %reg(val i4) %reg(val 0x4c6528) %reg(23)* %ccreg(val 0x4ddf50)*
|
||||
Before: 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
|
||||
|
||||
Live var sets before/after instruction setsw 10 %reg(val 0x4c6528)*
|
||||
Before: 0x4d6398(i4) 0x4d8290(i1)
|
||||
After : 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
|
||||
|
||||
Live var sets before/after instruction add %reg(val i2) %reg(val i3) %reg(val i4)*
|
||||
Before: 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
|
||||
After : 0x4d6398(i4) 0x4d8290(i1)
|
||||
|
||||
Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val i3)*
|
||||
Before: 0x4d8290(i1) 0x5ab450(i2)
|
||||
After : 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
|
||||
|
||||
Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
|
||||
Before: 0x4d8290(i1) 0x726c68(PhiCp:)
|
||||
After : 0x4d8290(i1) 0x5ab450(i2)
|
||||
|
||||
======For BB L1Done: Live var sets for instructions======
|
||||
|
||||
Live var sets before/after instruction nop
|
||||
Before:
|
||||
After :
|
||||
|
||||
Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4d6398
|
||||
Before: 0x4d6398(i4)
|
||||
After :
|
||||
Analysing live variables ...
|
||||
For BB 0x5ab498(bb0) :
|
||||
Defs: 0x4daa90 0x4f2d68 0x4f2df8 0x501768(result)
|
||||
In:
|
||||
Out:
|
||||
|
||||
After Backward Pass 0...
|
||||
For BB bb0:
|
||||
In:
|
||||
Out:
|
||||
Live Variable Analysis complete!
|
||||
|
||||
======For BB bb0: Live var sets for instructions======
|
||||
|
||||
Live var sets before/after instruction nop
|
||||
Before:
|
||||
After :
|
||||
|
||||
Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x501768
|
||||
Before: 0x501768(result)
|
||||
After :
|
||||
|
||||
Live var sets before/after instruction nop
|
||||
Before: 0x501768(result)
|
||||
After : 0x501768(result)
|
||||
|
||||
Live var sets before/after instruction call %disp(label PhiTest) Implicit:0x4f2d68 0x4f2df8 0x501768* 0x4daa90*
|
||||
Before: 0x4f2d68 0x4f2df8
|
||||
After : 0x501768(result)
|
||||
|
||||
Live var sets before/after instruction setsw 17 %reg(val 0x4f2df8)*
|
||||
Before: 0x4f2d68
|
||||
After : 0x4f2d68 0x4f2df8
|
||||
|
||||
Live var sets before/after instruction setsw 9 %reg(val 0x4f2d68)*
|
||||
Before:
|
||||
After : 0x4f2d68
|
||||
Loading…
Reference in New Issue