forked from OSchip/llvm-project
[RISCV] Add codegen support for RV64A
In order to support codegen RV64A, this patch: * Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg that use the i64 type. These are ultimately lowered to masked operations using lr.w/sc.w, but we need to use these alternate intrinsics for RV64 because i32 is not legal * Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and PseudoCmpXchg64 * Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as needed for RV64 and to select the i64 intrinsic IDs when necessary * Adds appropriate patterns to RISCVInstrInfoA.td * Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support This ends up being a fairly mechanical change, as the logic for RV32A is effectively reused. Differential Revision: https://reviews.llvm.org/D53233 llvm-svn: 351422
This commit is contained in:
Alex Bradbury
parent
b694030647
commit
07f1c62371
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@ -41,4 +41,29 @@ def int_riscv_masked_cmpxchg_i32
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llvm_i32_ty, llvm_i32_ty],
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[IntrArgMemOnly, NoCapture<0>]>;
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class MaskedAtomicRMW64Intrinsic
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: Intrinsic<[llvm_i64_ty],
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[llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
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[IntrArgMemOnly, NoCapture<0>]>;
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class MaskedAtomicRMW64WithSextIntrinsic
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: Intrinsic<[llvm_i64_ty],
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[llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
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llvm_i64_ty],
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[IntrArgMemOnly, NoCapture<0>]>;
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def int_riscv_masked_atomicrmw_xchg_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_atomicrmw_add_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_atomicrmw_sub_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_atomicrmw_nand_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_atomicrmw_max_i64 : MaskedAtomicRMW64WithSextIntrinsic;
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def int_riscv_masked_atomicrmw_min_i64 : MaskedAtomicRMW64WithSextIntrinsic;
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def int_riscv_masked_atomicrmw_umax_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_atomicrmw_umin_i64 : MaskedAtomicRMW64Intrinsic;
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def int_riscv_masked_cmpxchg_i64
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: Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty,
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llvm_i64_ty, llvm_i64_ty],
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[IntrArgMemOnly, NoCapture<0>]>;
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} // TargetPrefix = "riscv"
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@ -87,6 +87,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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case RISCV::PseudoAtomicLoadNand32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 32,
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NextMBBI);
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case RISCV::PseudoAtomicLoadNand64:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 64,
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NextMBBI);
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case RISCV::PseudoMaskedAtomicSwap32:
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return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, true, 32,
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NextMBBI);
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@ -111,6 +114,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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NextMBBI);
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case RISCV::PseudoCmpXchg32:
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return expandAtomicCmpXchg(MBB, MBBI, false, 32, NextMBBI);
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case RISCV::PseudoCmpXchg64:
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return expandAtomicCmpXchg(MBB, MBBI, false, 64, NextMBBI);
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case RISCV::PseudoMaskedCmpXchg32:
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return expandAtomicCmpXchg(MBB, MBBI, true, 32, NextMBBI);
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}
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@ -152,12 +157,61 @@ static unsigned getSCForRMW32(AtomicOrdering Ordering) {
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}
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}
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static unsigned getLRForRMW64(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::LR_D;
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case AtomicOrdering::Acquire:
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return RISCV::LR_D_AQ;
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case AtomicOrdering::Release:
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return RISCV::LR_D;
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case AtomicOrdering::AcquireRelease:
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return RISCV::LR_D_AQ;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::LR_D_AQ_RL;
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}
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}
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static unsigned getSCForRMW64(AtomicOrdering Ordering) {
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switch (Ordering) {
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default:
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llvm_unreachable("Unexpected AtomicOrdering");
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case AtomicOrdering::Monotonic:
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return RISCV::SC_D;
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case AtomicOrdering::Acquire:
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return RISCV::SC_D;
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case AtomicOrdering::Release:
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return RISCV::SC_D_RL;
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case AtomicOrdering::AcquireRelease:
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return RISCV::SC_D_RL;
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case AtomicOrdering::SequentiallyConsistent:
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return RISCV::SC_D_AQ_RL;
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}
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}
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static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
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if (Width == 32)
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return getLRForRMW32(Ordering);
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if (Width == 64)
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return getLRForRMW64(Ordering);
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llvm_unreachable("Unexpected LR width\n");
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}
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static unsigned getSCForRMW(AtomicOrdering Ordering, int Width) {
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if (Width == 32)
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return getSCForRMW32(Ordering);
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if (Width == 64)
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return getSCForRMW64(Ordering);
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llvm_unreachable("Unexpected SC width\n");
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}
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static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
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DebugLoc DL, MachineBasicBlock *ThisMBB,
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MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB,
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AtomicRMWInst::BinOp BinOp, int Width) {
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assert(Width == 32 && "RV64 atomic expansion currently unsupported");
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned ScratchReg = MI.getOperand(1).getReg();
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unsigned AddrReg = MI.getOperand(2).getReg();
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@ -166,11 +220,11 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
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static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
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// .loop:
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// lr.w dest, (addr)
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// lr.[w|d] dest, (addr)
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// binop scratch, dest, val
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// sc.w scratch, scratch, (addr)
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// sc.[w|d] scratch, scratch, (addr)
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// bnez scratch, loop
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BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
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BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
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.addReg(AddrReg);
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switch (BinOp) {
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default:
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@ -184,7 +238,7 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
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.addImm(-1);
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break;
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}
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BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
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BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
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.addReg(AddrReg)
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.addReg(ScratchReg);
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BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
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@ -219,7 +273,7 @@ static void doMaskedAtomicBinOpExpansion(
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const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
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MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width) {
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assert(Width == 32 && "RV64 atomic expansion currently unsupported");
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assert(Width == 32 && "Should never need to expand masked 64-bit operations");
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned ScratchReg = MI.getOperand(1).getReg();
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unsigned AddrReg = MI.getOperand(2).getReg();
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@ -333,7 +387,7 @@ bool RISCVExpandPseudo::expandAtomicMinMaxOp(
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MachineBasicBlock::iterator &NextMBBI) {
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assert(IsMasked == true &&
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"Should only need to expand masked atomic max/min");
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assert(Width == 32 && "RV64 atomic expansion currently unsupported");
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assert(Width == 32 && "Should never need to expand masked 64-bit operations");
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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@ -451,7 +505,6 @@ bool RISCVExpandPseudo::expandAtomicMinMaxOp(
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bool RISCVExpandPseudo::expandAtomicCmpXchg(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
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int Width, MachineBasicBlock::iterator &NextMBBI) {
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assert(Width == 32 && "RV64 atomic expansion currently unsupported");
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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@ -483,18 +536,18 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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if (!IsMasked) {
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// .loophead:
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// lr.w dest, (addr)
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// lr.[w|d] dest, (addr)
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// bne dest, cmpval, done
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BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
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BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
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.addReg(AddrReg);
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BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
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.addReg(DestReg)
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.addReg(CmpValReg)
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.addMBB(DoneMBB);
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// .looptail:
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// sc.w scratch, newval, (addr)
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// sc.[w|d] scratch, newval, (addr)
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// bnez scratch, loophead
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BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
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BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
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.addReg(AddrReg)
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.addReg(NewValReg);
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BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
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@ -507,7 +560,7 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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// and scratch, dest, mask
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// bne scratch, cmpval, done
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unsigned MaskReg = MI.getOperand(5).getReg();
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BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
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BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
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.addReg(AddrReg);
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BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
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.addReg(DestReg)
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@ -525,7 +578,7 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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// bnez scratch, loophead
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insertMaskedMerge(TII, DL, LoopTailMBB, ScratchReg, DestReg, NewValReg,
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MaskReg, ScratchReg);
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BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
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BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
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.addReg(AddrReg)
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.addReg(ScratchReg);
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BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
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@ -1728,37 +1728,74 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
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}
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static Intrinsic::ID
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getIntrinsicForMaskedAtomicRMWBinOp32(AtomicRMWInst::BinOp BinOp) {
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switch (BinOp) {
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default:
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llvm_unreachable("Unexpected AtomicRMW BinOp");
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case AtomicRMWInst::Xchg:
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return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
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case AtomicRMWInst::Add:
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return Intrinsic::riscv_masked_atomicrmw_add_i32;
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case AtomicRMWInst::Sub:
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return Intrinsic::riscv_masked_atomicrmw_sub_i32;
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case AtomicRMWInst::Nand:
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return Intrinsic::riscv_masked_atomicrmw_nand_i32;
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case AtomicRMWInst::Max:
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return Intrinsic::riscv_masked_atomicrmw_max_i32;
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case AtomicRMWInst::Min:
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return Intrinsic::riscv_masked_atomicrmw_min_i32;
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case AtomicRMWInst::UMax:
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return Intrinsic::riscv_masked_atomicrmw_umax_i32;
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case AtomicRMWInst::UMin:
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return Intrinsic::riscv_masked_atomicrmw_umin_i32;
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getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) {
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if (XLen == 32) {
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switch (BinOp) {
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default:
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llvm_unreachable("Unexpected AtomicRMW BinOp");
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case AtomicRMWInst::Xchg:
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return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
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case AtomicRMWInst::Add:
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return Intrinsic::riscv_masked_atomicrmw_add_i32;
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case AtomicRMWInst::Sub:
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return Intrinsic::riscv_masked_atomicrmw_sub_i32;
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case AtomicRMWInst::Nand:
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return Intrinsic::riscv_masked_atomicrmw_nand_i32;
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case AtomicRMWInst::Max:
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return Intrinsic::riscv_masked_atomicrmw_max_i32;
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case AtomicRMWInst::Min:
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return Intrinsic::riscv_masked_atomicrmw_min_i32;
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case AtomicRMWInst::UMax:
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return Intrinsic::riscv_masked_atomicrmw_umax_i32;
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case AtomicRMWInst::UMin:
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return Intrinsic::riscv_masked_atomicrmw_umin_i32;
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}
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}
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if (XLen == 64) {
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switch (BinOp) {
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default:
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llvm_unreachable("Unexpected AtomicRMW BinOp");
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case AtomicRMWInst::Xchg:
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return Intrinsic::riscv_masked_atomicrmw_xchg_i64;
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case AtomicRMWInst::Add:
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return Intrinsic::riscv_masked_atomicrmw_add_i64;
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case AtomicRMWInst::Sub:
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return Intrinsic::riscv_masked_atomicrmw_sub_i64;
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case AtomicRMWInst::Nand:
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return Intrinsic::riscv_masked_atomicrmw_nand_i64;
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case AtomicRMWInst::Max:
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return Intrinsic::riscv_masked_atomicrmw_max_i64;
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case AtomicRMWInst::Min:
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return Intrinsic::riscv_masked_atomicrmw_min_i64;
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case AtomicRMWInst::UMax:
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return Intrinsic::riscv_masked_atomicrmw_umax_i64;
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case AtomicRMWInst::UMin:
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return Intrinsic::riscv_masked_atomicrmw_umin_i64;
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}
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}
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llvm_unreachable("Unexpected XLen\n");
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}
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Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
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IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
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Value *Ordering = Builder.getInt32(static_cast<uint32_t>(AI->getOrdering()));
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unsigned XLen = Subtarget.getXLen();
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Value *Ordering =
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Builder.getIntN(XLen, static_cast<uint64_t>(AI->getOrdering()));
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Type *Tys[] = {AlignedAddr->getType()};
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Function *LrwOpScwLoop = Intrinsic::getDeclaration(
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AI->getModule(),
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getIntrinsicForMaskedAtomicRMWBinOp32(AI->getOperation()), Tys);
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getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys);
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if (XLen == 64) {
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Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty());
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Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
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ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty());
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}
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Value *Result;
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// Must pass the shift amount needed to sign extend the loaded value prior
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// to performing a signed comparison for min/max. ShiftAmt is the number of
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@ -1770,13 +1807,18 @@ Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
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const DataLayout &DL = AI->getModule()->getDataLayout();
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unsigned ValWidth =
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DL.getTypeStoreSizeInBits(AI->getValOperand()->getType());
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Value *SextShamt = Builder.CreateSub(
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Builder.getInt32(Subtarget.getXLen() - ValWidth), ShiftAmt);
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return Builder.CreateCall(LrwOpScwLoop,
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{AlignedAddr, Incr, Mask, SextShamt, Ordering});
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Value *SextShamt =
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Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt);
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Result = Builder.CreateCall(LrwOpScwLoop,
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{AlignedAddr, Incr, Mask, SextShamt, Ordering});
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} else {
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Result =
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Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
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}
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return Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
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if (XLen == 64)
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Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
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return Result;
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}
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TargetLowering::AtomicExpansionKind
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@ -1791,10 +1833,21 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
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Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
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IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
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Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
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Value *Ordering = Builder.getInt32(static_cast<uint32_t>(Ord));
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unsigned XLen = Subtarget.getXLen();
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Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
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Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32;
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if (XLen == 64) {
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CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty());
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NewVal = Builder.CreateSExt(NewVal, Builder.getInt64Ty());
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Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
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CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64;
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}
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Type *Tys[] = {AlignedAddr->getType()};
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Function *MaskedCmpXchg = Intrinsic::getDeclaration(
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CI->getModule(), Intrinsic::riscv_masked_cmpxchg_i32, Tys);
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return Builder.CreateCall(MaskedCmpXchg,
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{AlignedAddr, CmpVal, NewVal, Mask, Ordering});
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Function *MaskedCmpXchg =
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Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys);
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Value *Result = Builder.CreateCall(
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MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
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if (XLen == 64)
|
||||
Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
|
||||
return Result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
|
|||
|
||||
class PseudoCmpXchg
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, i32imm:$ordering), []> {
|
||||
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
|
|
@ -263,7 +263,7 @@ defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>;
|
|||
def PseudoMaskedCmpXchg32
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
|
||||
i32imm:$ordering), []> {
|
||||
ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
|
|
@ -276,3 +276,79 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
|
|||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, imm:$ordering)>;
|
||||
|
||||
} // Predicates = [HasStdExtA]
|
||||
|
||||
let Predicates = [HasStdExtA, IsRV64] in {
|
||||
|
||||
/// 64-bit atomic loads and stores
|
||||
|
||||
// Fences will be inserted for atomic load/stores according to the logic in
|
||||
// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
|
||||
defm : LdPat<atomic_load_64, LD>;
|
||||
defm : AtomicStPat<atomic_store_64, SD, GPR>;
|
||||
|
||||
defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
|
||||
defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;
|
||||
defm : AMOPat<"atomic_load_and_64", "AMOAND_D">;
|
||||
defm : AMOPat<"atomic_load_or_64", "AMOOR_D">;
|
||||
defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D">;
|
||||
defm : AMOPat<"atomic_load_max_64", "AMOMAX_D">;
|
||||
defm : AMOPat<"atomic_load_min_64", "AMOMIN_D">;
|
||||
defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D">;
|
||||
defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
|
||||
|
||||
/// 64-bit AMOs
|
||||
|
||||
def : Pat<(atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr),
|
||||
(AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_64_acquire GPR:$addr, GPR:$incr),
|
||||
(AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_64_release GPR:$addr, GPR:$incr),
|
||||
(AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr),
|
||||
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr),
|
||||
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
|
||||
/// 64-bit pseudo AMOs
|
||||
|
||||
def PseudoAtomicLoadNand64 : PseudoAMO;
|
||||
// Ordering constants must be kept in sync with the AtomicOrdering enum in
|
||||
// AtomicOrdering.h.
|
||||
def : Pat<(atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
|
||||
def : Pat<(atomic_load_nand_64_acquire GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
|
||||
def : Pat<(atomic_load_nand_64_release GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
|
||||
def : Pat<(atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
|
||||
def : Pat<(atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;
|
||||
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,
|
||||
PseudoMaskedAtomicSwap32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i64,
|
||||
PseudoMaskedAtomicLoadAdd32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i64,
|
||||
PseudoMaskedAtomicLoadSub32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i64,
|
||||
PseudoMaskedAtomicLoadNand32>;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i64,
|
||||
PseudoMaskedAtomicLoadMax32>;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i64,
|
||||
PseudoMaskedAtomicLoadMin32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i64,
|
||||
PseudoMaskedAtomicLoadUMax32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
|
||||
PseudoMaskedAtomicLoadUMin32>;
|
||||
|
||||
/// 64-bit compare and exchange
|
||||
|
||||
def PseudoCmpXchg64 : PseudoCmpXchg;
|
||||
defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64>;
|
||||
|
||||
def : Pat<(int_riscv_masked_cmpxchg_i64
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, imm:$ordering),
|
||||
(PseudoMaskedCmpXchg32
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, imm:$ordering)>;
|
||||
} // Predicates = [HasStdExtA, IsRV64]
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
; RUN: | FileCheck -check-prefix=RV32IA %s
|
||||
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64I %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64IA %s
|
||||
|
||||
define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
||||
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
|
||||
|
|
@ -56,6 +58,30 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB0_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB0_1
|
||||
; RV64IA-NEXT: .LBB0_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -110,6 +136,30 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB1_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB1_1
|
||||
; RV64IA-NEXT: .LBB1_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -164,6 +214,30 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB2_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB2_1
|
||||
; RV64IA-NEXT: .LBB2_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -218,6 +292,30 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB3_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB3_1
|
||||
; RV64IA-NEXT: .LBB3_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -272,6 +370,30 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_release_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB4_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB4_1
|
||||
; RV64IA-NEXT: .LBB4_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -326,6 +448,30 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB5_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB5_1
|
||||
; RV64IA-NEXT: .LBB5_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -380,6 +526,30 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB6_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB6_1
|
||||
; RV64IA-NEXT: .LBB6_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -434,6 +604,30 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB7_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB7_1
|
||||
; RV64IA-NEXT: .LBB7_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -488,6 +682,30 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB8_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB8_1
|
||||
; RV64IA-NEXT: .LBB8_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -542,6 +760,30 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: andi a3, a0, 3
|
||||
; RV64IA-NEXT: slli a3, a3, 3
|
||||
; RV64IA-NEXT: addi a4, zero, 255
|
||||
; RV64IA-NEXT: sllw a4, a4, a3
|
||||
; RV64IA-NEXT: andi a2, a2, 255
|
||||
; RV64IA-NEXT: sllw a2, a2, a3
|
||||
; RV64IA-NEXT: andi a1, a1, 255
|
||||
; RV64IA-NEXT: sllw a1, a1, a3
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: and a5, a3, a4
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB9_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a3, a2
|
||||
; RV64IA-NEXT: and a5, a5, a4
|
||||
; RV64IA-NEXT: xor a5, a3, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB9_1
|
||||
; RV64IA-NEXT: .LBB9_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
|
@ -597,6 +839,31 @@ define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB10_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB10_1
|
||||
; RV64IA-NEXT: .LBB10_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -652,6 +919,31 @@ define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB11_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB11_1
|
||||
; RV64IA-NEXT: .LBB11_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -707,6 +999,31 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB12_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB12_1
|
||||
; RV64IA-NEXT: .LBB12_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -762,6 +1079,31 @@ define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB13_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB13_1
|
||||
; RV64IA-NEXT: .LBB13_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -817,6 +1159,31 @@ define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_release_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB14_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB14_1
|
||||
; RV64IA-NEXT: .LBB14_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -872,6 +1239,31 @@ define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB15_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB15_1
|
||||
; RV64IA-NEXT: .LBB15_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -927,6 +1319,31 @@ define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB16_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB16_1
|
||||
; RV64IA-NEXT: .LBB16_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -982,6 +1399,31 @@ define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB17_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB17_1
|
||||
; RV64IA-NEXT: .LBB17_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1037,6 +1479,31 @@ define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB18_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB18_1
|
||||
; RV64IA-NEXT: .LBB18_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1092,6 +1559,31 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lui a3, 16
|
||||
; RV64IA-NEXT: addiw a3, a3, -1
|
||||
; RV64IA-NEXT: and a1, a1, a3
|
||||
; RV64IA-NEXT: and a2, a2, a3
|
||||
; RV64IA-NEXT: andi a4, a0, 3
|
||||
; RV64IA-NEXT: slli a4, a4, 3
|
||||
; RV64IA-NEXT: sllw a3, a3, a4
|
||||
; RV64IA-NEXT: sllw a2, a2, a4
|
||||
; RV64IA-NEXT: sllw a1, a1, a4
|
||||
; RV64IA-NEXT: andi a0, a0, -4
|
||||
; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
||||
; RV64IA-NEXT: and a5, a4, a3
|
||||
; RV64IA-NEXT: bne a5, a1, .LBB19_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
|
||||
; RV64IA-NEXT: xor a5, a4, a2
|
||||
; RV64IA-NEXT: and a5, a5, a3
|
||||
; RV64IA-NEXT: xor a5, a4, a5
|
||||
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
||||
; RV64IA-NEXT: bnez a5, .LBB19_1
|
||||
; RV64IA-NEXT: .LBB19_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1133,6 +1625,17 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB20_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB20_1
|
||||
; RV64IA-NEXT: .LBB20_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1174,6 +1677,17 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB21_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB21_1
|
||||
; RV64IA-NEXT: .LBB21_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1215,6 +1729,17 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB22_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB22_1
|
||||
; RV64IA-NEXT: .LBB22_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1256,6 +1781,17 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB23_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB23_1
|
||||
; RV64IA-NEXT: .LBB23_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1297,6 +1833,17 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_release_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB24_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB24_1
|
||||
; RV64IA-NEXT: .LBB24_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1338,6 +1885,17 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB25_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB25_1
|
||||
; RV64IA-NEXT: .LBB25_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1379,6 +1937,17 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB26_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB26_1
|
||||
; RV64IA-NEXT: .LBB26_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1420,6 +1989,17 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB27_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB27_1
|
||||
; RV64IA-NEXT: .LBB27_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1461,6 +2041,17 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB28_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB28_1
|
||||
; RV64IA-NEXT: .LBB28_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1502,6 +2093,17 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB29_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
|
||||
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB29_1
|
||||
; RV64IA-NEXT: .LBB29_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1551,6 +2153,17 @@ define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB30_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB30_1
|
||||
; RV64IA-NEXT: .LBB30_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1602,6 +2215,17 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB31_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB31_1
|
||||
; RV64IA-NEXT: .LBB31_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1651,6 +2275,17 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_acquire_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB32_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB32_1
|
||||
; RV64IA-NEXT: .LBB32_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1702,6 +2337,17 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_release_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB33_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB33_1
|
||||
; RV64IA-NEXT: .LBB33_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1753,6 +2399,17 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_release_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB34_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB34_1
|
||||
; RV64IA-NEXT: .LBB34_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1804,6 +2461,17 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB35_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB35_1
|
||||
; RV64IA-NEXT: .LBB35_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1855,6 +2523,17 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB36_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB36_1
|
||||
; RV64IA-NEXT: .LBB36_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1906,6 +2585,17 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB37_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB37_1
|
||||
; RV64IA-NEXT: .LBB37_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1957,6 +2647,17 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB38_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB38_1
|
||||
; RV64IA-NEXT: .LBB38_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
|
||||
ret void
|
||||
}
|
||||
|
|
@ -2006,6 +2707,17 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
|
||||
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
||||
; RV64IA-NEXT: bne a3, a1, .LBB39_3
|
||||
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
|
||||
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
||||
; RV64IA-NEXT: bnez a4, .LBB39_1
|
||||
; RV64IA-NEXT: .LBB39_3:
|
||||
; RV64IA-NEXT: ret
|
||||
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
; RUN: | FileCheck -check-prefix=RV32IA %s
|
||||
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64I %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64IA %s
|
||||
|
||||
define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
|
||||
; RV32I-LABEL: atomic_load_i8_unordered:
|
||||
|
|
@ -31,6 +33,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i8_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lb a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i8, i8* %a unordered, align 1
|
||||
ret i8 %1
|
||||
}
|
||||
|
|
@ -60,6 +67,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i8_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lb a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i8, i8* %a monotonic, align 1
|
||||
ret i8 %1
|
||||
}
|
||||
|
|
@ -90,6 +102,12 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i8_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lb a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i8, i8* %a acquire, align 1
|
||||
ret i8 %1
|
||||
}
|
||||
|
|
@ -121,6 +139,13 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i8_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, rw
|
||||
; RV64IA-NEXT: lb a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i8, i8* %a seq_cst, align 1
|
||||
ret i8 %1
|
||||
}
|
||||
|
|
@ -150,6 +175,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i16_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lh a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i16, i16* %a unordered, align 2
|
||||
ret i16 %1
|
||||
}
|
||||
|
|
@ -179,6 +209,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i16_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lh a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i16, i16* %a monotonic, align 2
|
||||
ret i16 %1
|
||||
}
|
||||
|
|
@ -209,6 +244,12 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i16_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lh a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i16, i16* %a acquire, align 2
|
||||
ret i16 %1
|
||||
}
|
||||
|
|
@ -240,6 +281,13 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i16_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, rw
|
||||
; RV64IA-NEXT: lh a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i16, i16* %a seq_cst, align 2
|
||||
ret i16 %1
|
||||
}
|
||||
|
|
@ -269,6 +317,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i32_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lw a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i32, i32* %a unordered, align 4
|
||||
ret i32 %1
|
||||
}
|
||||
|
|
@ -298,6 +351,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i32_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lw a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i32, i32* %a monotonic, align 4
|
||||
ret i32 %1
|
||||
}
|
||||
|
|
@ -328,6 +386,12 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i32_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: lw a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i32, i32* %a acquire, align 4
|
||||
ret i32 %1
|
||||
}
|
||||
|
|
@ -359,6 +423,13 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i32_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, rw
|
||||
; RV64IA-NEXT: lw a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i32, i32* %a seq_cst, align 4
|
||||
ret i32 %1
|
||||
}
|
||||
|
|
@ -393,6 +464,11 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i64_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: ld a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i64, i64* %a unordered, align 8
|
||||
ret i64 %1
|
||||
}
|
||||
|
|
@ -427,6 +503,11 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i64_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: ld a0, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i64, i64* %a monotonic, align 8
|
||||
ret i64 %1
|
||||
}
|
||||
|
|
@ -461,6 +542,12 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i64_acquire:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: ld a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i64, i64* %a acquire, align 8
|
||||
ret i64 %1
|
||||
}
|
||||
|
|
@ -495,6 +582,13 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_load_i64_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, rw
|
||||
; RV64IA-NEXT: ld a0, 0(a0)
|
||||
; RV64IA-NEXT: fence r, rw
|
||||
; RV64IA-NEXT: ret
|
||||
%1 = load atomic i64, i64* %a seq_cst, align 8
|
||||
ret i64 %1
|
||||
}
|
||||
|
|
@ -524,6 +618,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i8_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sb a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i8 %b, i8* %a unordered, align 1
|
||||
ret void
|
||||
}
|
||||
|
|
@ -553,6 +652,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i8_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sb a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i8 %b, i8* %a monotonic, align 1
|
||||
ret void
|
||||
}
|
||||
|
|
@ -583,6 +687,12 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i8_release:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sb a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i8 %b, i8* %a release, align 1
|
||||
ret void
|
||||
}
|
||||
|
|
@ -613,6 +723,12 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i8_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sb a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i8 %b, i8* %a seq_cst, align 1
|
||||
ret void
|
||||
}
|
||||
|
|
@ -642,6 +758,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i16_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sh a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a unordered, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -671,6 +792,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i16_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sh a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a monotonic, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -701,6 +827,12 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i16_release:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sh a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a release, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -731,6 +863,12 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i16_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sh a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -760,6 +898,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i32_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sw a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a unordered, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -789,6 +932,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i32_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sw a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a monotonic, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -819,6 +967,12 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i32_release:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sw a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a release, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -849,6 +1003,12 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i32_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sw a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a seq_cst, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -883,6 +1043,11 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i64_unordered:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sd a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a unordered, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -917,6 +1082,11 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i64_monotonic:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: sd a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a monotonic, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -951,6 +1121,12 @@ define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i64_release:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sd a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a release, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -985,6 +1161,12 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind {
|
|||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IA-LABEL: atomic_store_i64_seq_cst:
|
||||
; RV64IA: # %bb.0:
|
||||
; RV64IA-NEXT: fence rw, w
|
||||
; RV64IA-NEXT: sd a1, 0(a0)
|
||||
; RV64IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a seq_cst, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue