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[SelectionDAGBuilder] Fix ISD::FREEZE creation for structs with fields of different types. 

The previous code used the type of the first field for the VT
passed to getNode for every field.

I've based the implementation here off what is done in visitSelect
as it removes the need to special case aggregates.

Differential Revision: https://reviews.llvm.org/D77093
This commit is contained in:
Craig Topper 2020-04-06 10:22:50 -07:00
parent 77e2493602
commit 07ed1fb597
2 changed files with 27 additions and 16 deletions
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29
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -10537,22 +10537,19 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
}
void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
SDNodeFlags Flags;
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) return;
SmallVector<SDValue, 4> Values(NumValues);
SDValue Op = getValue(I.getOperand(0));
if (I.getOperand(0)->getType()->isAggregateType()) {
EVT VT = Op.getValueType();
SmallVector<SDValue, 1> Values;
for (unsigned i = 0; i < Op.getNumOperands(); ++i) {
SDValue Arg(Op.getNode(), i);
SDValue UnNodeValue = DAG.getNode(ISD::FREEZE, getCurSDLoc(), VT, Arg, Flags);
Values.push_back(UnNodeValue);
}
SDValue MergedValue = DAG.getMergeValues(Values, getCurSDLoc());
setValue(&I, MergedValue);
} else {
SDValue UnNodeValue = DAG.getNode(ISD::FREEZE, getCurSDLoc(), Op.getValueType(),
Op, Flags);
setValue(&I, UnNodeValue);
}
for (unsigned i = 0; i != NumValues; ++i)
Values[i] = DAG.getNode(ISD::FREEZE, getCurSDLoc(), ValueVTs[i],
SDValue(Op.getNode(), Op.getResNo() + i));
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(ValueVTs), Values));
}

14
llvm/test/CodeGen/X86/freeze.ll
View File

@ -97,6 +97,20 @@ define i32 @freeze_anonstruct() {
ret i32 %t1
}
define i32 @freeze_anonstruct2() {
; X86ASM-LABEL: freeze_anonstruct2:
; X86ASM: # %bb.0:
; X86ASM-NEXT: movzwl %ax, %eax
; X86ASM-NEXT: addl %eax, %eax
; X86ASM-NEXT: retq
%y1 = freeze {i32, i16} undef
%v1 = extractvalue {i32, i16} %y1, 0
%v2 = extractvalue {i32, i16} %y1, 1
%z2 = zext i16 %v2 to i32
%t1 = add i32 %v1, %z2
ret i32 %t1
}
define i64 @freeze_array() {
; X86ASM-LABEL: freeze_array:
; X86ASM: # %bb.0: