forked from OSchip/llvm-project
parent
24e8f0cfe6
commit
07a34a5f69
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@ -150,7 +150,6 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MBB->push_back(MI);
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MBB->push_back(MI);
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return ResultReg;
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return ResultReg;
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}
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}
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@ -162,9 +161,7 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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MBB->push_back(MI);
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MBB->push_back(MI);
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return ResultReg;
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return ResultReg;
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}
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}
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@ -176,10 +173,7 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0).addReg(Op1);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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MI->addOperand(MachineOperand::CreateReg(Op1, false));
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MBB->push_back(MI);
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MBB->push_back(MI);
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return ResultReg;
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return ResultReg;
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}
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}
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