forked from OSchip/llvm-project
[X86] Group setOperationActions related to vXi1 masks together. NFCI
Previously they were sort of interleaved in with XMM/YMM/ZMM action related code. Trying to separate things so its easier to split 512-bit vectors later. llvm-svn: 320781
This commit is contained in:
Craig Topper
parent
b89bc20a64
commit
07a28f777e
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@ -1147,6 +1147,49 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
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addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
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setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v16i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Custom);
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// Extends of v16i1/v8i1 to 128-bit vectors.
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v8i16, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v8i16, Custom);
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for (auto VT : { MVT::v8i1, MVT::v16i1 }) {
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setOperationAction(ISD::ADD, VT, Custom);
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setOperationAction(ISD::SUB, VT, Custom);
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setOperationAction(ISD::MUL, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Expand);
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}
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
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for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1,
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MVT::v16i1, MVT::v32i1, MVT::v64i1 })
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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for (MVT VT : MVT::fp_vector_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
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@ -1188,14 +1231,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v16i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Custom);
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setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
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setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
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@ -1214,8 +1249,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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}
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if (Subtarget.hasAVX512())
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setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
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if (Subtarget.hasDQI()) {
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for (auto VT : { MVT::v2i64, MVT::v4i64, MVT::v8i64 }) {
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@ -1235,14 +1268,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
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// Extends of v16i1/v8i1 to 128-bit vectors.
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v8i16, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v8i16, Custom);
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for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
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setOperationAction(ISD::FFLOOR, VT, Legal);
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setOperationAction(ISD::FCEIL, VT, Legal);
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@ -1262,7 +1287,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
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setOperationAction(ISD::MUL, MVT::v8i64, Custom);
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setOperationAction(ISD::MUL, MVT::v16i32, Legal);
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@ -1270,10 +1294,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::UMUL_LOHI, MVT::v16i32, Custom);
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setOperationAction(ISD::SMUL_LOHI, MVT::v16i32, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
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@ -1283,21 +1303,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::ABS, MVT::v4i64, Legal);
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setOperationAction(ISD::ABS, MVT::v2i64, Legal);
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for (auto VT : { MVT::v8i1, MVT::v16i1 }) {
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setOperationAction(ISD::ADD, VT, Custom);
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setOperationAction(ISD::SUB, VT, Custom);
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setOperationAction(ISD::MUL, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Expand);
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}
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for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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@ -1362,7 +1367,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 })
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setOperationAction(ISD::MSCATTER, VT, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v1i1, Legal);
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// Extract subvector is special because the value type
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// (result) is 256-bit but the source is 512-bit wide.
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@ -1370,9 +1374,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
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MVT::v8f32, MVT::v4f64 })
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1,
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MVT::v16i1, MVT::v32i1, MVT::v64i1 })
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
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for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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@ -1400,61 +1401,57 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
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addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
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setOperationAction(ISD::ADD, MVT::v32i1, Custom);
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setOperationAction(ISD::ADD, MVT::v64i1, Custom);
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setOperationAction(ISD::SUB, MVT::v32i1, Custom);
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setOperationAction(ISD::SUB, MVT::v64i1, Custom);
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setOperationAction(ISD::MUL, MVT::v32i1, Custom);
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setOperationAction(ISD::MUL, MVT::v64i1, Custom);
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for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
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setOperationAction(ISD::ADD, VT, Custom);
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setOperationAction(ISD::SUB, VT, Custom);
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setOperationAction(ISD::MUL, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::TRUNCATE, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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}
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
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// Extends from v32i1 masks to 256-bit vectors.
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setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
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// Extends from v64i1 masks to 512-bit vectors.
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setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
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setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
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setOperationAction(ISD::MUL, MVT::v32i16, Legal);
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setOperationAction(ISD::MUL, MVT::v64i8, Custom);
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setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
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setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
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setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
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setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i1, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i1, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
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setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v32i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v32i1, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v64i1, Custom);
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setOperationAction(ISD::VSELECT, MVT::v32i1, Expand);
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setOperationAction(ISD::VSELECT, MVT::v64i1, Expand);
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setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
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