forked from OSchip/llvm-project
Remove a few more calls to TargetMachine::getSubtarget from the
R600 port. llvm-svn: 229804
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7edca437f5
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0795a2ef0c
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@ -26,7 +26,7 @@ using namespace llvm;
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void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
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assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
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DAG = static_cast<ScheduleDAGMILive*>(dag);
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const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &ST = DAG->MF.getSubtarget<AMDGPUSubtarget>();
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TII = static_cast<const R600InstrInfo*>(DAG->TII);
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TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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VLIW5 = !ST.hasCaymanISA();
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@ -39,8 +39,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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unsigned FrameIndex,
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unsigned SubIdx) {
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const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>(
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MF->getTarget().getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
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MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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@ -70,7 +70,7 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
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const MachineFunction &MF) const {
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const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
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// FIXME: We should get this information from kernel attributes if it
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// is available.
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return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();
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