forked from OSchip/llvm-project
AMDGPU: Select scratch mubuf offsets when pointer is a constant
In call sequence setups, there may not be a frame index base and the pointer is a constant offset from the frame pointer / scratch wave offset register. llvm-svn: 301230
This commit is contained in:
Matt Arsenault
parent
df6539f44b
commit
0774ea267a
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@ -116,8 +116,11 @@ private:
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bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
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SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
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SDValue &SLC) const;
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bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
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SDValue &SOffset, SDValue &ImmOffset) const;
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bool SelectMUBUFScratchOffen(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
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SDValue &SOffset, SDValue &ImmOffset) const;
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bool SelectMUBUFScratchOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
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SDValue &Offset) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
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SDValue &Offset, SDValue &GLC, SDValue &SLC,
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SDValue &TFE) const;
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@ -953,8 +956,12 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
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return true;
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}
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static bool isLegalMUBUFImmOffset(unsigned Imm) {
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return isUInt<12>(Imm);
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}
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static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
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return isUInt<12>(Imm->getZExtValue());
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return isLegalMUBUFImmOffset(Imm->getZExtValue());
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}
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bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
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@ -1076,9 +1083,9 @@ SDValue AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
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return N;
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}
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bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
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SDValue &VAddr, SDValue &SOffset,
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SDValue &ImmOffset) const {
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bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDValue Addr, SDValue &Rsrc,
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SDValue &VAddr, SDValue &SOffset,
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SDValue &ImmOffset) const {
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SDLoc DL(Addr);
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MachineFunction &MF = CurDAG->getMachineFunction();
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@ -1087,8 +1094,22 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
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Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
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SOffset = CurDAG->getRegister(Info->getScratchWaveOffsetReg(), MVT::i32);
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// (add n0, c1)
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if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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unsigned Imm = CAddr->getZExtValue();
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assert(!isLegalMUBUFImmOffset(Imm) &&
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"should have been selected by other pattern");
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SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
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MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
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DL, MVT::i32, HighBits);
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VAddr = SDValue(MovHighBits, 0);
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ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
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return true;
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}
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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// (add n0, c1)
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SDValue N0 = Addr.getOperand(0);
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SDValue N1 = Addr.getOperand(1);
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@ -1107,6 +1128,24 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDValue Addr,
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SDValue &SRsrc,
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SDValue &SOffset,
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SDValue &Offset) const {
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ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr);
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if (!CAddr || !isLegalMUBUFImmOffset(CAddr))
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return false;
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SDLoc DL(Addr);
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MachineFunction &MF = CurDAG->getMachineFunction();
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const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
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SOffset = CurDAG->getRegister(Info->getScratchWaveOffsetReg(), MVT::i32);
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Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
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SDValue &SOffset, SDValue &Offset,
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SDValue &GLC, SDValue &SLC,
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@ -11,7 +11,9 @@ def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
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def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
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def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
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def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
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def MUBUFScratchOffen : ComplexPattern<i64, 4, "SelectMUBUFScratchOffen">;
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def MUBUFScratchOffset : ComplexPattern<i64, 3, "SelectMUBUFScratchOffset", [], [], 20>;
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def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
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def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">;
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def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
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@ -958,21 +960,30 @@ defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>;
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} // End Predicates = [Has16BitInsts]
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class MUBUFScratchLoadPat <MUBUF_Pseudo Instr, ValueType vt, PatFrag ld> : Pat <
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(vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset))),
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(Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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multiclass MUBUFScratchLoadPat <MUBUF_Pseudo InstrOffen,
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MUBUF_Pseudo InstrOffset,
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ValueType vt, PatFrag ld> {
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def : Pat <
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(vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset))),
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(InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i16, sextloadi8_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i16, extloadi8_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
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def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
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def : Pat <
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(vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))),
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(InstrOffset $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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}
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i32, sextloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i32, extloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i16, extloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, BUFFER_LOAD_SSHORT_OFFSET, i32, sextloadi16_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, BUFFER_LOAD_USHORT_OFFSET, i32, extloadi16_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, BUFFER_LOAD_DWORD_OFFSET, i32, load_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, BUFFER_LOAD_DWORDX2_OFFSET, v2i32, load_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, BUFFER_LOAD_DWORDX4_OFFSET, v4i32, load_private>;
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// BUFFER_LOAD_DWORD*, addr64=0
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multiclass MUBUF_Load_Dword <ValueType vt,
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@ -1054,19 +1065,29 @@ multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
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defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>;
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defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, global_store>;
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class MUBUFScratchStorePat <MUBUF_Pseudo Instr, ValueType vt, PatFrag st> : Pat <
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(st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
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u16imm:$offset)),
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(Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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multiclass MUBUFScratchStorePat <MUBUF_Pseudo InstrOffen,
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MUBUF_Pseudo InstrOffset,
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ValueType vt, PatFrag st> {
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def : Pat <
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(st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset)),
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(InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i16, truncstorei8_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i16, store_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
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def : Pat <
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(st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset,
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u16imm:$offset)),
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(InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0)
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>;
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}
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defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i32, truncstorei8_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i32, truncstorei16_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i16, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, BUFFER_STORE_DWORD_OFFSET, i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, BUFFER_STORE_DWORDX2_OFFSET, v2i32, store_private>;
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defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, BUFFER_STORE_DWORDX4_OFFSET, v4i32, store_private>;
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//===----------------------------------------------------------------------===//
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// MTBUF Patterns
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=HSA -check-prefix=CI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=HSA -check-prefix=GFX9 %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
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; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
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; HSA: enable_sgpr_private_segment_buffer = 1
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@ -223,9 +223,8 @@ define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
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}
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; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
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; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], 0{{$}}
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
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; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
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define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
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%cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(0)*
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store volatile i32 7, i32* %cast
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@ -0,0 +1,136 @@
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; RUN: llc -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; Test addressing modes when the scratch base is not a frame index.
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; GCN-LABEL: {{^}}store_private_offset_i8:
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; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @store_private_offset_i8() #0 {
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store volatile i8 5, i8* inttoptr (i32 8 to i8*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i16:
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; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @store_private_offset_i16() #0 {
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store volatile i16 5, i16* inttoptr (i32 8 to i16*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i32:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @store_private_offset_i32() #0 {
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store volatile i32 5, i32* inttoptr (i32 8 to i32*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_v2i32:
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; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @store_private_offset_v2i32() #0 {
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store volatile <2 x i32> <i32 5, i32 10>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_v4i32:
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; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @store_private_offset_v4i32() #0 {
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store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*)
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i8:
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @load_private_offset_i8() #0 {
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%load = load volatile i8, i8* inttoptr (i32 8 to i8*)
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ret void
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}
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; GCN-LABEL: {{^}}sextload_private_offset_i8:
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; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
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%load = load volatile i8, i8* inttoptr (i32 8 to i8*)
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%sextload = sext i8 %load to i32
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store i32 %sextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}zextload_private_offset_i8:
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
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%load = load volatile i8, i8* inttoptr (i32 8 to i8*)
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%zextload = zext i8 %load to i32
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store i32 %zextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i16:
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; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @load_private_offset_i16() #0 {
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%load = load volatile i16, i16* inttoptr (i32 8 to i16*)
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ret void
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}
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; GCN-LABEL: {{^}}sextload_private_offset_i16:
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; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
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%load = load volatile i16, i16* inttoptr (i32 8 to i16*)
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%sextload = sext i16 %load to i32
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store i32 %sextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}zextload_private_offset_i16:
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; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8
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define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
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%load = load volatile i16, i16* inttoptr (i32 8 to i16*)
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%zextload = zext i16 %load to i32
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store i32 %zextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i32:
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], s8 offset:8
|
||||
define amdgpu_kernel void @load_private_offset_i32() #0 {
|
||||
%load = load volatile i32, i32* inttoptr (i32 8 to i32*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_offset_v2i32:
|
||||
; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s8 offset:8
|
||||
define amdgpu_kernel void @load_private_offset_v2i32() #0 {
|
||||
%load = load volatile <2 x i32>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_offset_v4i32:
|
||||
; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s8 offset:8
|
||||
define amdgpu_kernel void @load_private_offset_v4i32() #0 {
|
||||
%load = load volatile <4 x i32>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:
|
||||
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s8 offset:4095
|
||||
define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {
|
||||
store volatile i8 5, i8* inttoptr (i32 4095 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1:
|
||||
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
|
||||
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s8 offen{{$}}
|
||||
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {
|
||||
store volatile i8 5, i8* inttoptr (i32 4096 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2:
|
||||
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
|
||||
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s8 offen offset:1{{$}}
|
||||
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
|
||||
store volatile i8 5, i8* inttoptr (i32 4097 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
|
||||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s
|
||||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
|
||||
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=OPTNONE %s
|
||||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
|
||||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s
|
||||
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
|
||||
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=OPTNONE %s
|
||||
|
||||
; There are no stack objects, but still a private memory access. The
|
||||
; private access regiters need to be correctly initialized anyway, and
|
||||
|
|
@ -27,9 +27,9 @@ define amdgpu_kernel void @store_to_undef() #0 {
|
|||
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
|
||||
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
|
||||
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s7{{$}}
|
||||
; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
|
||||
; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
|
||||
define amdgpu_kernel void @store_to_inttoptr() #0 {
|
||||
store volatile i32 0, i32* inttoptr (i32 123 to i32*)
|
||||
store volatile i32 0, i32* inttoptr (i32 124 to i32*)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -47,9 +47,9 @@ define amdgpu_kernel void @load_from_undef() #0 {
|
|||
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
|
||||
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
|
||||
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s7{{$}}
|
||||
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
|
||||
; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
|
||||
define amdgpu_kernel void @load_from_inttoptr() #0 {
|
||||
%ld = load volatile i32, i32* inttoptr (i32 123 to i32*)
|
||||
%ld = load volatile i32, i32* inttoptr (i32 124 to i32*)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue