R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips

llvm-svn: 180759

llvm/lib/Target/R600/Processors.td

@@ -13,37 +13,37 @@
 
 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
 : Processor<Name, itin, Features>;
-def : Proc<"",           R600_EG_Itin,
+def : Proc<"",           R600_VLIW5_Itin,
     [FeatureR600ALUInst, FeatureVertexCache]>;
-def : Proc<"r600",       R600_EG_Itin,
+def : Proc<"r600",       R600_VLIW5_Itin,
     [FeatureR600ALUInst , FeatureVertexCache]>;
-def : Proc<"rs880",      R600_EG_Itin,
+def : Proc<"rs880",      R600_VLIW5_Itin,
     [FeatureR600ALUInst]>;
-def : Proc<"rv670",      R600_EG_Itin,
+def : Proc<"rv670",      R600_VLIW5_Itin,
     [FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>;
-def : Proc<"rv710",      R600_EG_Itin,
+def : Proc<"rv710",      R600_VLIW5_Itin,
     [FeatureVertexCache]>;
-def : Proc<"rv730",      R600_EG_Itin,
+def : Proc<"rv730",      R600_VLIW5_Itin,
     [FeatureVertexCache]>;
-def : Proc<"rv770",      R600_EG_Itin,
+def : Proc<"rv770",      R600_VLIW5_Itin,
     [FeatureFP64, FeatureVertexCache]>;
-def : Proc<"cedar",      R600_EG_Itin,
+def : Proc<"cedar",      R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
-def : Proc<"redwood",    R600_EG_Itin,
+def : Proc<"redwood",    R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
-def : Proc<"sumo",       R600_EG_Itin,
+def : Proc<"sumo",       R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages]>;
-def : Proc<"juniper",    R600_EG_Itin,
+def : Proc<"juniper",    R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
-def : Proc<"cypress",    R600_EG_Itin,
+def : Proc<"cypress",    R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>;
-def : Proc<"barts",      R600_EG_Itin,
+def : Proc<"barts",      R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
-def : Proc<"turks",      R600_EG_Itin,
+def : Proc<"turks",      R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
-def : Proc<"caicos",     R600_EG_Itin,
+def : Proc<"caicos",     R600_VLIW5_Itin,
     [FeatureByteAddress, FeatureImages]>;
-def : Proc<"cayman",     R600_EG_Itin,
+def : Proc<"cayman",     R600_VLIW4_Itin,
     [FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI",         SI_Itin, [Feature64BitPtr, FeatureFP64]>;
 def : Proc<"tahiti",     SI_Itin, [Feature64BitPtr, FeatureFP64]>;
 def : Proc<"pitcairn",   SI_Itin, [Feature64BitPtr, FeatureFP64]>;

llvm/lib/Target/R600/R600InstrInfo.cpp

@@ -140,6 +140,14 @@ bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
           (TargetFlags & R600_InstFlag::OP3));
 }
 
+bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
+  return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
+}
+
+bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
+  return isTransOnly(MI->getOpcode());
+}
+
 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
   return ST.hasVertexCache() && get(Opcode).TSFlags & R600_InstFlag::VTX_INST;
 }

llvm/lib/Target/R600/R600InstrInfo.h

@@ -54,6 +54,9 @@ namespace llvm {
   /// \returns true if this \p Opcode represents an ALU instruction.
   bool isALUInstr(unsigned Opcode) const;
 
+  bool isTransOnly(unsigned Opcode) const;
+  bool isTransOnly(const MachineInstr *MI) const;
+
   bool usesVertexCache(unsigned Opcode) const;
   bool usesVertexCache(const MachineInstr *MI) const;
   bool usesTextureCache(unsigned Opcode) const;

llvm/lib/Target/R600/R600Instructions.td

@@ -18,6 +18,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
     : AMDGPUInst <outs, ins, asm, pattern> {
 
   field bits<64> Inst;
+  bit TransOnly = 0;
   bit Trig = 0;
   bit Op3 = 0;
   bit isVector = 0;
@@ -35,6 +36,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
   let Pattern = pattern;
   let Itinerary = itin;
 
+  let TSFlags{0} = TransOnly;
   let TSFlags{4} = Trig;
   let TSFlags{5} = Op3;
 
@@ -1301,23 +1303,38 @@ multiclass CUBE_Common <bits<11> inst> {
 
 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "EXP_IEEE", fexp2
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "FLT_TO_INT", fp_to_sint
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "INT_TO_FLT", sint_to_fp
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "FLT_TO_UINT", fp_to_uint
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "UINT_TO_FLT", uint_to_fp
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
   inst, "LOG_CLAMPED", []
@@ -1325,50 +1342,84 @@ class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
 
 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "LOG_IEEE", flog2
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
   inst, "MULHI_INT", mulhs
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
   inst, "MULHI", mulhu
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
   inst, "MULLO_INT", mul
->;
-class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
+class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
   inst, "RECIP_CLAMPED", []
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
   inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "RECIP_UINT", AMDGPUurecip
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
   inst, "RECIPSQRT_IEEE", []
->;
+> {
+  let TransOnly = 1;
+  let Itinerary = TransALU;
+}
 
 class SIN_Common <bits<11> inst> : R600_1OP <
   inst, "SIN", []>{
   let Trig = 1;
+  let TransOnly = 1;
+  let Itinerary = TransALU;
 }
 
 class COS_Common <bits<11> inst> : R600_1OP <
   inst, "COS", []> {
   let Trig = 1;
+  let TransOnly = 1;
+  let Itinerary = TransALU;
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/R600/R600Schedule.td

@@ -24,7 +24,7 @@ def AnyALU : InstrItinClass;
 def VecALU : InstrItinClass;
 def TransALU : InstrItinClass;
 
-def R600_EG_Itin : ProcessorItineraries <
+def R600_VLIW5_Itin : ProcessorItineraries <
   [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
   [],
   [
@@ -34,3 +34,14 @@ def R600_EG_Itin : ProcessorItineraries <
     InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
   ]
 >;
+
+def R600_VLIW4_Itin : ProcessorItineraries <
+  [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL],
+  [],
+  [
+    InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
+    InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
+    InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
+    InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
+  ]
+>;