forked from OSchip/llvm-project
Fixed the namespace to match SparcInternals.h; added notes on some missing
sections of instructions. llvm-svn: 6448
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@ -13,7 +13,7 @@
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class InstV9 : Instruction { // Sparc instruction baseline
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field bits<32> Inst;
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set Namespace = "SparcV9";
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set Namespace = "V9";
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bits<2> op;
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set Inst{31-30} = op; // Top two bits are the 'op' field
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@ -202,7 +202,16 @@ def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
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def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
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def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
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// Section A.24: Jump and Link
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// FIXME: A.20: Flush Instruction Memory - p167
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// FIXME: A.21: Flush Register Windows - p169
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// A.22: Illegal instruction Trap - p170
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// Not used
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// A.23: Implementation-Dependent Instructions - p171
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// Not used
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// Section A.24: Jump and Link - p172
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// Mimicking the Sparc's instr def...
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def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
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def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
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@ -319,11 +328,14 @@ def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
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def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
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#endif
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// Section A.34: Move F-P Register on Integer Register (FMOVr)
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// FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr)
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// Section A.35: Move Integer Register on Condition (MOVcc)
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// Section A.36: Move Integer Register on Register Condition (MOVR)
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// FIXME: Section A.35: Move Integer Register on Condition (MOVcc)
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// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
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// Section A.37: Multiply and Divide (64-bit) - p199
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def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
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@ -425,6 +437,7 @@ def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
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def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
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// Section A.50: FIXME
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// Section A.51: FIXME
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// Section A.52: Store Floating-point -p225
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