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[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI. 

The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.

llvm-svn: 319006
This commit is contained in:
Craig Topper 2017-11-26 21:14:48 +00:00
parent fe6e92d517
commit 074003c8e2
1 changed files with 1 additions and 2 deletions
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3
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -2149,8 +2149,7 @@ static void Passv64i1ArgInRegs(
const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
CCValAssign &NextVA, const X86Subtarget &Subtarget) { CCValAssign &NextVA, const X86Subtarget &Subtarget) {
assert((Subtarget.hasBWI() || Subtarget.hasBMI()) && assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
"Expected AVX512BW or AVX512BMI target!");
assert(Subtarget.is32Bit() && "Expecting 32 bit target"); assert(Subtarget.is32Bit() && "Expecting 32 bit target");
assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value"); assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
assert(VA.isRegLoc() && NextVA.isRegLoc() && assert(VA.isRegLoc() && NextVA.isRegLoc() &&