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[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU. 

llvm-svn: 331473
This commit is contained in:
Simon Pilgrim 2018-05-03 18:22:49 +00:00
parent f2d2cedab4
commit 0720c8d90e
2 changed files with 4 additions and 17 deletions
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3
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -9842,9 +9842,8 @@ multiclass avx512_unary_lowering<string InstrStr, SDNode OpNode,
}
}
// FIXME: Is there a better scheduler class for VPLZCNT?
defm VPLZCNT : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz,
SchedWriteVecALU, HasCDI>;
SchedWriteVecIMul, HasCDI>;
// FIXME: Is there a better scheduler class for VPCONFLICT?
defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict,

18
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -1249,13 +1249,7 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PSYrr",
"VCVTUDQ2PSZrr",
"VCVTUQQ2PDZ128rr",
"VCVTUQQ2PDZ256rr",
"VCVTUQQ2PDZrr",
"VPLZCNTDZ128rr",
"VPLZCNTDZ256rr",
"VPLZCNTDZrr",
"VPLZCNTQZ128rr",
"VPLZCNTQZ256rr",
"VPLZCNTQZrr")>;
"VCVTUQQ2PDZrr")>;
def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
let Latency = 4;
@ -2681,9 +2675,7 @@ def: InstRW<[SKXWriteResGroup149], (instregex "CVTDQ2PSrm",
"VCVTUDQ2PDZ128rm(b?)",
"VCVTUDQ2PSZ128rm(b?)",
"VCVTUQQ2PDZ128rm(b?)",
"VCVTUQQ2PSZ128rm(b?)",
"VPLZCNTDZ128rm(b?)",
"VPLZCNTQZ128rm(b?)")>;
"VCVTUQQ2PSZ128rm(b?)")>;
def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 10;
@ -2807,11 +2799,7 @@ def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PDZ256rm(b?)",
"VCVTUDQ2PSZrm(b?)",
"VCVTUQQ2PDZ256rm(b?)",
"VCVTUQQ2PDZrm(b?)",
"VCVTUQQ2PSZ256rm(b?)",
"VPLZCNTDZ256rm(b?)",
"VPLZCNTDZrm(b?)",
"VPLZCNTQZ256rm(b?)",
"VPLZCNTQZrm(b?)")>;
"VCVTUQQ2PSZ256rm(b?)")>;
def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 11;