forked from OSchip/llvm-project
[RISCV] Reserve an emergency spill slot for the register scavenger when necessary
Although the register scavenger can often find a spare register, an emergency spill slot is needed to guarantee success. Reserve this slot in cases where the function is known to have a large stack (meaning the scavenger may be needed when forming stack addresses). llvm-svn: 322269
This commit is contained in:
Alex Bradbury
parent
da45439fba
commit
0715d35ed5
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@ -18,6 +18,7 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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using namespace llvm;
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@ -224,3 +225,21 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
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SavedRegs.set(RISCV::X1);
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SavedRegs.set(RISCV::X8);
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}
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void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
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MachineFunction &MF, RegScavenger *RS) const {
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const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetRegisterClass *RC = &RISCV::GPRRegClass;
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// estimateStackSize has been observed to under-estimate the final stack
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// size, so give ourselves wiggle-room by checking for stack size
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// representable an 11-bit signed field rather than 12-bits.
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// FIXME: It may be possible to craft a function with a small stack that
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// still needs an emergency spill slot for branch relaxation. This case
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// would currently be missed.
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if (!isInt<11>(MFI.estimateStackSize(MF))) {
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int RegScavFI = MFI.CreateStackObject(
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RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);
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RS->addScavengingFrameIndex(RegScavFI);
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}
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}
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@ -36,6 +36,9 @@ public:
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS) const override;
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bool hasFP(const MachineFunction &MF) const override;
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MachineBasicBlock::iterator
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@ -8,31 +8,116 @@ define void @test() nounwind {
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; RV32I-LABEL: test:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1664
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; RV32I-NEXT: addi a0, a0, 1680
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1660
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; RV32I-NEXT: addi a0, a0, 1676
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: sw ra, 0(a0)
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1656
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; RV32I-NEXT: addi a0, a0, 1672
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: sw s0, 0(a0)
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1664
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; RV32I-NEXT: addi a0, a0, 1680
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; RV32I-NEXT: add s0, sp, a0
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1656
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; RV32I-NEXT: addi a0, a0, 1672
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw s0, 0(a0)
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1660
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; RV32I-NEXT: addi a0, a0, 1676
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw ra, 0(a0)
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a0, a0, 1664
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; RV32I-NEXT: addi a0, a0, 1680
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: ret
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%tmp = alloca [ 305419896 x i8 ] , align 4
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ret void
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}
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; This test case artificially produces register pressure which should force
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; use of the emergency spill slot.
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define void @test_emergency_spill_slot(i32 %a) nounwind {
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; RV32I-LABEL: test_emergency_spill_slot:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1376
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; RV32I-NEXT: sub sp, sp, a1
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1380
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; RV32I-NEXT: add a1, sp, a1
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; RV32I-NEXT: sw ra, 0(a1)
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1384
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; RV32I-NEXT: add a1, sp, a1
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; RV32I-NEXT: sw s0, 0(a1)
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1388
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; RV32I-NEXT: add a1, sp, a1
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; RV32I-NEXT: sw s1, 0(a1)
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1392
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; RV32I-NEXT: add a1, sp, a1
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; RV32I-NEXT: sw s2, 0(a1)
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; RV32I-NEXT: lui a1, 98
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; RV32I-NEXT: addi a1, a1, -1376
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; RV32I-NEXT: add s0, sp, a1
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; RV32I-NEXT: lui a1, 78
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; RV32I-NEXT: addi a1, a1, 512
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; RV32I-NEXT: lui a2, 1048478
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; RV32I-NEXT: addi a2, a2, 1388
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; RV32I-NEXT: add a2, s0, a2
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; RV32I-NEXT: mv a2, a2
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; RV32I-NEXT: add a1, a2, a1
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; RV32I-NEXT: #APP
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; RV32I-NEXT: nop
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: sw a0, 0(a1)
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; RV32I-NEXT: #APP
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; RV32I-NEXT: nop
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: lui a0, 98
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; RV32I-NEXT: addi a0, a0, -1392
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw s2, 0(a0)
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; RV32I-NEXT: lui a0, 98
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; RV32I-NEXT: addi a0, a0, -1388
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw s1, 0(a0)
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; RV32I-NEXT: lui a0, 98
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; RV32I-NEXT: addi a0, a0, -1384
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw s0, 0(a0)
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; RV32I-NEXT: lui a0, 98
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; RV32I-NEXT: addi a0, a0, -1380
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lw ra, 0(a0)
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; RV32I-NEXT: lui a0, 98
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; RV32I-NEXT: addi a0, a0, -1376
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: ret
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%data = alloca [ 100000 x i32 ] , align 4
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
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%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
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%asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
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%asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
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%asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
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%asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
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%asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
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%asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
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%asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
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%asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
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%asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
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%asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
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%asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
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%asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
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%asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
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%asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
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store volatile i32 %a, i32* %ptr
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tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
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ret void
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}
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