forked from OSchip/llvm-project
compactify some more instruction definitions
llvm-svn: 27288
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parent
45c709388a
commit
070181c927
llvm/lib/Target/PowerPC
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@ -306,35 +306,13 @@ def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VRLB : VXForm_1<4, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlb VRRC:$vA, VRRC:$vB))]>;
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def VRLH : VXForm_1<68, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlh VRRC:$vA, VRRC:$vB))]>;
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def VRLW : VXForm_1<132, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlw VRRC:$vA, VRRC:$vB))]>;
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def VSLO : VXForm_1<1036, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslo $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslo VRRC:$vA, VRRC:$vB))]>;
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def VSLB : VXForm_1<260, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslb VRRC:$vA, VRRC:$vB))]>;
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def VSLH : VXForm_1<324, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslh VRRC:$vA, VRRC:$vB))]>;
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def VSLW : VXForm_1<388, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslw VRRC:$vA, VRRC:$vB))]>;
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def VRLB : VX1_Int< 4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
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def VRLH : VX1_Int< 68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
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def VRLW : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
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def VSLO : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
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def VSLB : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
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def VSLH : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
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def VSLW : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
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def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltb $vD, $vB, $UIMM", VecPerm,
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@ -347,38 +325,14 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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def VSR : VXForm_1<708, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsr $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsr VRRC:$vA, VRRC:$vB))]>;
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def VSRO : VXForm_1<1100, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsro $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsro VRRC:$vA, VRRC:$vB))]>;
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def VSRAB : VXForm_1<772, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrab $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrab VRRC:$vA, VRRC:$vB))]>;
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def VSRAH : VXForm_1<836, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrah $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrah VRRC:$vA, VRRC:$vB))]>;
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def VSRAW : VXForm_1<900, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsraw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsraw VRRC:$vA, VRRC:$vB))]>;
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def VSRB : VXForm_1<516, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrb VRRC:$vA, VRRC:$vB))]>;
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def VSRH : VXForm_1<580, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrh VRRC:$vA, VRRC:$vB))]>;
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def VSRW : VXForm_1<644, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrw VRRC:$vA, VRRC:$vB))]>;
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def VSR : VX1_Int< 708, "vsr $vD, $vA, $vB" , int_ppc_altivec_vsr>;
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def VSRO : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
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def VSRAB : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
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def VSRAH : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
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def VSRAW : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
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def VSRB : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
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def VSRH : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
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def VSRW : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
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def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
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