forked from OSchip/llvm-project
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
This commit is contained in:
Sean Fertile
parent
5d67fb3ecc
commit
06c810b155
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@ -1,16 +1,18 @@
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
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; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
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; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM32PWR4 %s
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
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; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
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; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s
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%struct.S1 = type { [1 x i8] }
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@gS1 = external global %struct.S1, align 1
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@ -34,13 +36,13 @@ declare void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1)
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; CHECKASM-LABEL: .call_test_byval_1Byte:
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; ASM32PWR4: stwu 1, -64(1)
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; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32PWR4-NEXT: lbz 3, 0([[REG]])
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; ASM32PWR4-NEXT: slwi 3, 3, 24
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; ASM32PWR4-NEXT: bl .test_byval_1Byte
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; ASM32PWR4-NEXT: nop
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; ASM32PWR4-NEXT: addi 1, 1, 64
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-NEXT: lbz 3, 0([[REG]])
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; ASM32-NEXT: slwi 3, 3, 24
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; ASM32-NEXT: bl .test_byval_1Byte
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; ASM32-NEXT: nop
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; ASM32-NEXT: addi 1, 1, 64
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
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@ -49,14 +51,14 @@ declare void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1)
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; ASM64PWR4: std 0, 16(1)
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; ASM64PWR4-NEXT: stdu 1, -112(1)
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; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64PWR4-NEXT: lbz 3, 0([[REG]])
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; ASM64PWR4-NEXT: sldi 3, 3, 56
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; ASM64PWR4-NEXT: bl .test_byval_1Byte
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; ASM64PWR4-NEXT: nop
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; ASM64PWR4-NEXT: addi 1, 1, 112
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; ASM64: std 0, 16(1)
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; ASM64-NEXT: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-NEXT: lbz 3, 0([[REG]])
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; ASM64-NEXT: sldi 3, 3, 56
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; ASM64-NEXT: bl .test_byval_1Byte
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; ASM64-NEXT: nop
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; ASM64-NEXT: addi 1, 1, 112
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%struct.S2 = type { [2 x i8] }
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@ -81,13 +83,13 @@ declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
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; CHECKASM-LABEL: .call_test_byval_2Byte:
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; ASM32PWR4: stwu 1, -64(1)
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; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32PWR4-NEXT: lhz 3, 0([[REG]])
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; ASM32PWR4-NEXT: slwi 3, 3, 16
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; ASM32PWR4-NEXT: bl .test_byval_2Byte
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; ASM32PWR4-NEXT: nop
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; ASM32PWR4-NEXT: addi 1, 1, 64
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-NEXT: lhz 3, 0([[REG]])
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; ASM32-NEXT: slwi 3, 3, 16
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; ASM32-NEXT: bl .test_byval_2Byte
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; ASM32-NEXT: nop
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; ASM32-NEXT: addi 1, 1, 64
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS2, $x2 :: (load 8 from got)
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@ -96,14 +98,14 @@ declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; ASM64PWR4: std 0, 16(1)
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; ASM64PWR4-NEXT: stdu 1, -112(1)
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; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64PWR4-NEXT: lhz 3, 0([[REG]])
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; ASM64PWR4-NEXT: sldi 3, 3, 48
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; ASM64PWR4-NEXT: bl .test_byval_2Byte
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; ASM64PWR4-NEXT: nop
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; ASM64PWR4-NEXT: addi 1, 1, 112
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; ASM64: std 0, 16(1)
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; ASM64-NEXT: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-NEXT: lhz 3, 0([[REG]])
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; ASM64-NEXT: sldi 3, 3, 48
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; ASM64-NEXT: bl .test_byval_2Byte
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; ASM64-NEXT: nop
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; ASM64-NEXT: addi 1, 1, 112
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%struct.S3 = type { [3 x i8] }
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@ -132,14 +134,14 @@ declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
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; CHECKASM-LABEL: .call_test_byval_3Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM32PWR4: stwu 1, -64(1)
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; ASM32PWR4-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32PWR4-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM32PWR4-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
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; ASM32PWR4-DAG: rlwinm 3, [[REG2]], 8, 16, 23
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; ASM32PWR4-DAG: rlwimi 3, [[REG1]], 16, 0, 15
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; ASM32PWR4-NEXT: bl .test_byval_3Byte
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; ASM32PWR4-NEXT: nop
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
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; ASM32-DAG: rlwinm 3, [[REG2]], 8, 16, 23
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; ASM32-DAG: rlwimi 3, [[REG1]], 16, 0, 15
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; ASM32-NEXT: bl .test_byval_3Byte
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; ASM32-NEXT: nop
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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@ -152,14 +154,14 @@ declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM64PWR4: stdu 1, -112(1)
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; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64PWR4-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM64PWR4-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
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; ASM64PWR4-DAG: rldic 3, [[REG2]], 40, 16
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; ASM64PWR4-DAG: rldimi 3, [[REG1]], 48, 0
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; ASM64PWR4-NEXT: bl .test_byval_3Byte
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; ASM64PWR4-NEXT: nop
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; ASM64: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
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; ASM64-DAG: rldic 3, [[REG2]], 40, 16
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; ASM64-DAG: rldimi 3, [[REG1]], 48, 0
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; ASM64-NEXT: bl .test_byval_3Byte
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; ASM64-NEXT: nop
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%struct.S4 = type { [4 x i8] }
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@ -183,12 +185,12 @@ declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1)
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; CHECKASM-LABEL: .call_test_byval_4Byte:
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; ASM32PWR4: stwu 1, -64(1)
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; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32PWR4-NEXT: lwz 3, 0([[REG]])
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; ASM32PWR4-NEXT: bl .test_byval_4Byte
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; ASM32PWR4-NEXT: nop
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; ASM32PWR4-NEXT: addi 1, 1, 64
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-NEXT: lwz 3, 0([[REG]])
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; ASM32-NEXT: bl .test_byval_4Byte
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; ASM32-NEXT: nop
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; ASM32-NEXT: addi 1, 1, 64
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
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@ -197,10 +199,10 @@ declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1)
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; ASM64PWR4: stdu 1, -112(1)
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; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64PWR4-NEXT: lwz 3, 0([[REG]])
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; ASM64PWR4-NEXT: sldi 3, 3, 32
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; ASM64PWR4-NEXT: bl .test_byval_4Byte
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; ASM64PWR4-NEXT: nop
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; ASM64PWR4-NEXT: addi 1, 1, 112
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; ASM64: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-NEXT: lwz 3, 0([[REG]])
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; ASM64-NEXT: sldi 3, 3, 32
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; ASM64-NEXT: bl .test_byval_4Byte
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; ASM64-NEXT: nop
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; ASM64-NEXT: addi 1, 1, 112
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@ -1,9 +1,10 @@
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
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; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
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; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
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; RUN: FileCheck --check-prefix=ASM %s
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%struct.S5 = type { [5 x i8] }
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@ -19,27 +20,27 @@ declare void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
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; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
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; CHECKASM-LABEL: .call_test_byval_5Byte:
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; ASM-LABEL: .call_test_byval_5Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
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; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
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; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
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; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
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; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
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; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
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; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM64PWR4: stdu 1, -112(1)
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; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM64PWR4-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
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; ASM64PWR4-DAG: rlwinm 3, [[REG2]], 24, 0, 7
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; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
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; ASM64PWR4-NEXT: bl .test_byval_5Byte
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; ASM64PWR4-NEXT: nop
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; ASM: stdu 1, -112(1)
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; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
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; ASM-DAG: rlwinm 3, [[REG2]], 24, 0, 7
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; ASM-DAG: rldimi 3, [[REG1]], 32, 0
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; ASM-NEXT: bl .test_byval_5Byte
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; ASM-NEXT: nop
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%struct.S6 = type { [6 x i8] }
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@ -55,27 +56,27 @@ declare void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
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; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
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; CHECKASM-LABEL: .call_test_byval_6Byte:
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; ASM-LABEL: .call_test_byval_6Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
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; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
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; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
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; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
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; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
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; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
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; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM64PWR4: stdu 1, -112(1)
|
||||
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM64PWR4-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM64PWR4-DAG: rlwinm 3, [[REG2]], 16, 0, 15
|
||||
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM64PWR4-NEXT: bl .test_byval_6Byte
|
||||
; ASM64PWR4-NEXT: nop
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM-DAG: rlwinm 3, [[REG2]], 16, 0, 15
|
||||
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM-NEXT: bl .test_byval_6Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
%struct.S7 = type { [7 x i8] }
|
||||
|
||||
|
|
@ -91,31 +92,31 @@ declare void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
|
|||
|
||||
; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_7Byte:
|
||||
; ASM-LABEL: .call_test_byval_7Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
|
||||
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
|
||||
; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
|
||||
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
|
||||
; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
|
||||
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
|
||||
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
|
||||
; CHECK-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
|
||||
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
|
||||
; CHECK-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
|
||||
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM64PWR4: stdu 1, -112(1)
|
||||
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM64PWR4-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM64PWR4-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
|
||||
; ASM64PWR4-DAG: rlwinm 3, [[REG3]], 8, 16, 23
|
||||
; ASM64PWR4-DAG: rlwimi 3, [[REG2]], 16, 0, 15
|
||||
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM64PWR4-NEXT: bl .test_byval_7Byte
|
||||
; ASM64PWR4-NEXT: nop
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
|
||||
; ASM-DAG: rlwinm 3, [[REG3]], 8, 16, 23
|
||||
; ASM-DAG: rlwimi 3, [[REG2]], 16, 0, 15
|
||||
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM-NEXT: bl .test_byval_7Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
%struct.S8 = type { [8 x i8] }
|
||||
|
||||
|
|
@ -131,16 +132,16 @@ declare void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
|
|||
|
||||
; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_8Byte:
|
||||
; ASM-LABEL: .call_test_byval_8Byte:
|
||||
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
|
||||
; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
|
||||
; CHECK-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; ASM64PWR4: stdu 1, -112(1)
|
||||
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64PWR4-NEXT: ld 3, 0([[REGADDR]])
|
||||
; ASM64PWR4-NEXT: bl .test_byval_8Byte
|
||||
; ASM64PWR4-NEXT: nop
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-NEXT: ld 3, 0([[REGADDR]])
|
||||
; ASM-NEXT: bl .test_byval_8Byte
|
||||
; ASM-NEXT: nop
|
||||
|
|
|
|||
Loading…
Reference in New Issue