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[X86] Add masked variable tests for funnel undef/zero argument combines 

I've avoided 'modulo' masks as we'll SimplifyDemandedBits those in the future, and we just need to check that the shift variable is 'in range'

llvm-svn: 353644
This commit is contained in:
Simon Pilgrim 2019-02-10 15:46:32 +00:00
parent d1307ec4cc
commit 06a61b0b2b
1 changed files with 90 additions and 0 deletions
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90
llvm/test/CodeGen/X86/funnel-shift.ll
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@ -378,6 +378,28 @@ define i32 @fshl_i32_undef0(i32 %a0, i32 %a1) nounwind {
ret i32 %res
}
define i32 @fshl_i32_undef0_msk(i32 %a0, i32 %a1) nounwind {
; X32-SSE2-LABEL: fshl_i32_undef0_msk:
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: andl $7, %ecx
; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; X32-SSE2-NEXT: shldl %cl, %eax, %eax
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshl_i32_undef0_msk:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: movl %esi, %ecx
; X64-AVX2-NEXT: andl $7, %ecx
; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shldl %cl, %edi, %eax
; X64-AVX2-NEXT: retq
%m = and i32 %a1, 7
%res = call i32 @llvm.fshl.i32(i32 undef, i32 %a0, i32 %m)
ret i32 %res
}
define i32 @fshl_i32_undef0_cst(i32 %a0) nounwind {
; X32-SSE2-LABEL: fshl_i32_undef0_cst:
; X32-SSE2: # %bb.0:
@ -412,6 +434,29 @@ define i32 @fshl_i32_undef1(i32 %a0, i32 %a1) nounwind {
ret i32 %res
}
define i32 @fshl_i32_undef1_msk(i32 %a0, i32 %a1) nounwind {
; X32-SSE2-LABEL: fshl_i32_undef1_msk:
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: andl $7, %ecx
; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; X32-SSE2-NEXT: shldl %cl, %eax, %eax
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshl_i32_undef1_msk:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: movl %esi, %ecx
; X64-AVX2-NEXT: movl %edi, %eax
; X64-AVX2-NEXT: andl $7, %ecx
; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shldl %cl, %eax, %eax
; X64-AVX2-NEXT: retq
%m = and i32 %a1, 7
%res = call i32 @llvm.fshl.i32(i32 %a0, i32 undef, i32 %m)
ret i32 %res
}
define i32 @fshl_i32_undef1_cst(i32 %a0) nounwind {
; X32-SSE2-LABEL: fshl_i32_undef1_cst:
; X32-SSE2: # %bb.0:
@ -464,6 +509,29 @@ define i32 @fshr_i32_undef0(i32 %a0, i32 %a1) nounwind {
ret i32 %res
}
define i32 @fshr_i32_undef0_msk(i32 %a0, i32 %a1) nounwind {
; X32-SSE2-LABEL: fshr_i32_undef0_msk:
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: andl $7, %ecx
; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; X32-SSE2-NEXT: shrdl %cl, %eax, %eax
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshr_i32_undef0_msk:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: movl %esi, %ecx
; X64-AVX2-NEXT: movl %edi, %eax
; X64-AVX2-NEXT: andl $7, %ecx
; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shrdl %cl, %eax, %eax
; X64-AVX2-NEXT: retq
%m = and i32 %a1, 7
%res = call i32 @llvm.fshr.i32(i32 undef, i32 %a0, i32 %m)
ret i32 %res
}
define i32 @fshr_i32_undef0_cst(i32 %a0) nounwind {
; X32-SSE2-LABEL: fshr_i32_undef0_cst:
; X32-SSE2: # %bb.0:
@ -498,6 +566,28 @@ define i32 @fshr_i32_undef1(i32 %a0, i32 %a1) nounwind {
ret i32 %res
}
define i32 @fshr_i32_undef1_msk(i32 %a0, i32 %a1) nounwind {
; X32-SSE2-LABEL: fshr_i32_undef1_msk:
; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: andl $7, %ecx
; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
; X32-SSE2-NEXT: shrdl %cl, %eax, %eax
; X32-SSE2-NEXT: retl
;
; X64-AVX2-LABEL: fshr_i32_undef1_msk:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: movl %esi, %ecx
; X64-AVX2-NEXT: andl $7, %ecx
; X64-AVX2-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-AVX2-NEXT: shrdl %cl, %edi, %eax
; X64-AVX2-NEXT: retq
%m = and i32 %a1, 7
%res = call i32 @llvm.fshr.i32(i32 %a0, i32 undef, i32 %m)
ret i32 %res
}
define i32 @fshr_i32_undef1_cst(i32 %a0) nounwind {
; X32-SSE2-LABEL: fshr_i32_undef1_cst:
; X32-SSE2: # %bb.0: