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[LegalizeVectorOps] Simplify the non-byte sized load handling VectorLegalizer::ExpandLoad. NFCI 

Remove an if that should always be true. Merge the body of another into the only block that could make the if true.

llvm-svn: 354654
This commit is contained in:
Craig Topper 2019-02-22 06:18:33 +00:00
parent 0ca023b3b7
commit 069cf05e87
1 changed files with 8 additions and 11 deletions
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19
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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@ -663,14 +663,12 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
unsigned WideBits = WideVT.getSizeInBits();
for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
SDValue Lo, Hi, ShAmt;
assert(BitOffset < WideBits && "Unexpected offset!");
if (BitOffset < WideBits) {
ShAmt = DAG.getConstant(
BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
}
SDValue ShAmt = DAG.getConstant(
BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
SDValue Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
BitOffset += SrcEltBits;
if (BitOffset >= WideBits) {
@ -680,14 +678,13 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
ShAmt = DAG.getConstant(
SrcEltBits - BitOffset, dl,
TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
SDValue Hi =
DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
}
}
if (Hi.getNode())
Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
switch (ExtType) {
default: llvm_unreachable("Unknown extended-load op!");
case ISD::EXTLOAD: