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[AArch64][SVE] Asm: Fix predicate pattern diagnostics. 

This patch uses the DiagnosticPredicate for SVE predicate patterns
to improve their diagnostics, now giving a 'invalid operand' diagnostic
if the type is not an immediate or one of the expected pattern
labels.

Reviewers: samparker, SjoerdMeijer, javed.absar, fhahn

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D48220

llvm-svn: 334983
This commit is contained in:
Sander de Smalen 2018-06-18 21:03:02 +00:00
parent d914fd2163
commit 067eee1c13
27 changed files with 90 additions and 88 deletions
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10
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -573,14 +573,16 @@ public:
return DiagnosticPredicateTy::NearMatch; return DiagnosticPredicateTy::NearMatch;
} }
bool isSVEPattern() const { DiagnosticPredicate isSVEPattern() const {
if (!isImm()) if (!isImm())
return false; return DiagnosticPredicateTy::NoMatch;
auto *MCE = dyn_cast<MCConstantExpr>(getImm()); auto *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE) if (!MCE)
return false; return DiagnosticPredicateTy::NoMatch;
int64_t Val = MCE->getValue(); int64_t Val = MCE->getValue();
return Val >= 0 && Val < 32; if (Val >= 0 && Val < 32)
return DiagnosticPredicateTy::Match;
return DiagnosticPredicateTy::NearMatch;
} }
bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const { bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const {

4
llvm/test/MC/AArch64/SVE/decb-diagnostics.s
View File

@ -37,12 +37,12 @@ decb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
decb x0, vl512 decb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decb x0, vl512 // CHECK-NEXT: decb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
decb x0, vl9 decb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decb x0, vl9 // CHECK-NEXT: decb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/decd-diagnostics.s
View File

@ -37,12 +37,12 @@ decd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
decd x0, vl512 decd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decd x0, vl512 // CHECK-NEXT: decd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
decd x0, vl9 decd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decd x0, vl9 // CHECK-NEXT: decd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/dech-diagnostics.s
View File

@ -37,12 +37,12 @@ dech x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
dech x0, vl512 dech x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: dech x0, vl512 // CHECK-NEXT: dech x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
dech x0, vl9 dech x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: dech x0, vl9 // CHECK-NEXT: dech x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/decw-diagnostics.s
View File

@ -37,12 +37,12 @@ decw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
decw x0, vl512 decw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decw x0, vl512 // CHECK-NEXT: decw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
decw x0, vl9 decw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: decw x0, vl9 // CHECK-NEXT: decw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/incb-diagnostics.s
View File

@ -37,12 +37,12 @@ incb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
incb x0, vl512 incb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incb x0, vl512 // CHECK-NEXT: incb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incb x0, vl9 incb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incb x0, vl9 // CHECK-NEXT: incb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/incd-diagnostics.s
View File

@ -37,12 +37,12 @@ incd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
incd x0, vl512 incd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incd x0, vl512 // CHECK-NEXT: incd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incd x0, vl9 incd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incd x0, vl9 // CHECK-NEXT: incd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/inch-diagnostics.s
View File

@ -37,12 +37,12 @@ inch x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
inch x0, vl512 inch x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: inch x0, vl512 // CHECK-NEXT: inch x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
inch x0, vl9 inch x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: inch x0, vl9 // CHECK-NEXT: inch x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/incw-diagnostics.s
View File

@ -37,12 +37,12 @@ incw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
incw x0, vl512 incw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incw x0, vl512 // CHECK-NEXT: incw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
incw x0, vl9 incw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: incw x0, vl9 // CHECK-NEXT: incw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/ptrue-diagnostics.s
View File

@ -5,12 +5,12 @@
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
ptrue p0.s, vl512 ptrue p0.s, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ptrue p0.s, vl512 // CHECK-NEXT: ptrue p0.s, vl512
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
ptrue p0.s, vl9 ptrue p0.s, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ptrue p0.s, vl9 // CHECK-NEXT: ptrue p0.s, vl9
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:

4
llvm/test/MC/AArch64/SVE/ptrues-diagnostics.s
View File

@ -5,12 +5,12 @@
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
ptrues p0.s, vl512 ptrues p0.s, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ptrues p0.s, vl512 // CHECK-NEXT: ptrues p0.s, vl512
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
ptrues p0.s, vl9 ptrues p0.s, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ptrues p0.s, vl9 // CHECK-NEXT: ptrues p0.s, vl9
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s
View File

@ -28,7 +28,7 @@ sqdecb x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, x1 sqdecb x0, x1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, x1 // CHECK-NEXT: sqdecb x0, x1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqdecb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqdecb x0, vl512 sqdecb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, vl512 // CHECK-NEXT: sqdecb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, vl9 sqdecb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, vl9 // CHECK-NEXT: sqdecb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s
View File

@ -28,7 +28,7 @@ sqdecd x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecd x0, x1 sqdecd x0, x1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecd x0, x1 // CHECK-NEXT: sqdecd x0, x1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqdecd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqdecd x0, vl512 sqdecd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecd x0, vl512 // CHECK-NEXT: sqdecd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecd x0, vl9 sqdecd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecd x0, vl9 // CHECK-NEXT: sqdecd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s
View File

@ -28,7 +28,7 @@ sqdech x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdech x0, x1 sqdech x0, x1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdech x0, x1 // CHECK-NEXT: sqdech x0, x1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqdech x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqdech x0, vl512 sqdech x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdech x0, vl512 // CHECK-NEXT: sqdech x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdech x0, vl9 sqdech x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdech x0, vl9 // CHECK-NEXT: sqdech x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s
View File

@ -28,7 +28,7 @@ sqdecw x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecw x0, x1 sqdecw x0, x1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecw x0, x1 // CHECK-NEXT: sqdecw x0, x1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqdecw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqdecw x0, vl512 sqdecw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecw x0, vl512 // CHECK-NEXT: sqdecw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecw x0, vl9 sqdecw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecw x0, vl9 // CHECK-NEXT: sqdecw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s
View File

@ -28,7 +28,7 @@ sqincb x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincb x0, x0 sqincb x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincb x0, x0 // CHECK-NEXT: sqincb x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqincb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqincb x0, vl512 sqincb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincb x0, vl512 // CHECK-NEXT: sqincb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincb x0, vl9 sqincb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincb x0, vl9 // CHECK-NEXT: sqincb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s
View File

@ -28,7 +28,7 @@ sqincd x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincd x0, x0 sqincd x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincd x0, x0 // CHECK-NEXT: sqincd x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqincd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqincd x0, vl512 sqincd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincd x0, vl512 // CHECK-NEXT: sqincd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincd x0, vl9 sqincd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincd x0, vl9 // CHECK-NEXT: sqincd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s
View File

@ -28,7 +28,7 @@ sqinch x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqinch x0, x0 sqinch x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqinch x0, x0 // CHECK-NEXT: sqinch x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqinch x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqinch x0, vl512 sqinch x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqinch x0, vl512 // CHECK-NEXT: sqinch x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqinch x0, vl9 sqinch x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqinch x0, vl9 // CHECK-NEXT: sqinch x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

6
llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s
View File

@ -28,7 +28,7 @@ sqincw x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincw x0, x0 sqincw x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincw x0, x0 // CHECK-NEXT: sqincw x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ sqincw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
sqincw x0, vl512 sqincw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincw x0, vl512 // CHECK-NEXT: sqincw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqincw x0, vl9 sqincw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqincw x0, vl9 // CHECK-NEXT: sqincw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s
View File

@ -18,17 +18,17 @@ uqdecb sp
// Operands not matching up (unsigned dec only has one register operand) // Operands not matching up (unsigned dec only has one register operand)
uqdecb x0, w0 uqdecb x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecb x0, w0 // CHECK-NEXT: uqdecb x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecb w0, w0 uqdecb w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecb w0, w0 // CHECK-NEXT: uqdecb w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecb x0, x0 uqdecb x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecb x0, x0 // CHECK-NEXT: uqdecb x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqdecb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqdecb x0, vl512 uqdecb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecb x0, vl512 // CHECK-NEXT: uqdecb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecb x0, vl9 uqdecb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecb x0, vl9 // CHECK-NEXT: uqdecb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s
View File

@ -18,17 +18,17 @@ uqdecd sp
// Operands not matching up (unsigned dec only has one register operand) // Operands not matching up (unsigned dec only has one register operand)
uqdecd x0, w0 uqdecd x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecd x0, w0 // CHECK-NEXT: uqdecd x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecd w0, w0 uqdecd w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecd w0, w0 // CHECK-NEXT: uqdecd w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecd x0, x0 uqdecd x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecd x0, x0 // CHECK-NEXT: uqdecd x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqdecd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqdecd x0, vl512 uqdecd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecd x0, vl512 // CHECK-NEXT: uqdecd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecd x0, vl9 uqdecd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecd x0, vl9 // CHECK-NEXT: uqdecd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s
View File

@ -18,17 +18,17 @@ uqdech sp
// Operands not matching up (unsigned dec only has one register operand) // Operands not matching up (unsigned dec only has one register operand)
uqdech x0, w0 uqdech x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdech x0, w0 // CHECK-NEXT: uqdech x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdech w0, w0 uqdech w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdech w0, w0 // CHECK-NEXT: uqdech w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdech x0, x0 uqdech x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdech x0, x0 // CHECK-NEXT: uqdech x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqdech x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqdech x0, vl512 uqdech x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdech x0, vl512 // CHECK-NEXT: uqdech x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdech x0, vl9 uqdech x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdech x0, vl9 // CHECK-NEXT: uqdech x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s
View File

@ -18,17 +18,17 @@ uqdecw sp
// Operands not matching up (unsigned dec only has one register operand) // Operands not matching up (unsigned dec only has one register operand)
uqdecw x0, w0 uqdecw x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecw x0, w0 // CHECK-NEXT: uqdecw x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecw w0, w0 uqdecw w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecw w0, w0 // CHECK-NEXT: uqdecw w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecw x0, x0 uqdecw x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecw x0, x0 // CHECK-NEXT: uqdecw x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqdecw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqdecw x0, vl512 uqdecw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecw x0, vl512 // CHECK-NEXT: uqdecw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqdecw x0, vl9 uqdecw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqdecw x0, vl9 // CHECK-NEXT: uqdecw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s
View File

@ -18,17 +18,17 @@ uqincb sp
// Operands not matching up (unsigned inc only has one register operand) // Operands not matching up (unsigned inc only has one register operand)
uqincb x0, w0 uqincb x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincb x0, w0 // CHECK-NEXT: uqincb x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincb w0, w0 uqincb w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincb w0, w0 // CHECK-NEXT: uqincb w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincb x0, x0 uqincb x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincb x0, x0 // CHECK-NEXT: uqincb x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqincb x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqincb x0, vl512 uqincb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincb x0, vl512 // CHECK-NEXT: uqincb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincb x0, vl9 uqincb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincb x0, vl9 // CHECK-NEXT: uqincb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s
View File

@ -18,17 +18,17 @@ uqincd sp
// Operands not matching up (unsigned inc only has one register operand) // Operands not matching up (unsigned inc only has one register operand)
uqincd x0, w0 uqincd x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincd x0, w0 // CHECK-NEXT: uqincd x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincd w0, w0 uqincd w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincd w0, w0 // CHECK-NEXT: uqincd w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincd x0, x0 uqincd x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincd x0, x0 // CHECK-NEXT: uqincd x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqincd x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqincd x0, vl512 uqincd x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincd x0, vl512 // CHECK-NEXT: uqincd x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincd x0, vl9 uqincd x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincd x0, vl9 // CHECK-NEXT: uqincd x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s
View File

@ -18,17 +18,17 @@ uqinch sp
// Operands not matching up (unsigned inc only has one register operand) // Operands not matching up (unsigned inc only has one register operand)
uqinch x0, w0 uqinch x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqinch x0, w0 // CHECK-NEXT: uqinch x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqinch w0, w0 uqinch w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqinch w0, w0 // CHECK-NEXT: uqinch w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqinch x0, x0 uqinch x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqinch x0, x0 // CHECK-NEXT: uqinch x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqinch x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqinch x0, vl512 uqinch x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqinch x0, vl512 // CHECK-NEXT: uqinch x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqinch x0, vl9 uqinch x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqinch x0, vl9 // CHECK-NEXT: uqinch x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

10
llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s
View File

@ -18,17 +18,17 @@ uqincw sp
// Operands not matching up (unsigned inc only has one register operand) // Operands not matching up (unsigned inc only has one register operand)
uqincw x0, w0 uqincw x0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincw x0, w0 // CHECK-NEXT: uqincw x0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincw w0, w0 uqincw w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincw w0, w0 // CHECK-NEXT: uqincw w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincw x0, x0 uqincw x0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincw x0, x0 // CHECK-NEXT: uqincw x0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@ -56,12 +56,12 @@ uqincw x0, all, mul #17
// Invalid predicate patterns // Invalid predicate patterns
uqincw x0, vl512 uqincw x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincw x0, vl512 // CHECK-NEXT: uqincw x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqincw x0, vl9 uqincw x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: uqincw x0, vl9 // CHECK-NEXT: uqincw x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: