forked from OSchip/llvm-project
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
Do not break down local loads and stores so ds_read/write_b96/b128 in ISelLowering can be selected on subtargets that support them and if align requirements allow them. Differential Revision: https://reviews.llvm.org/D84403
This commit is contained in:
Mirko Brkusanin
parent
d17ea67b92
commit
0654ff703d
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@ -667,6 +667,11 @@ public:
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return CIInsts && EnableDS128;
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}
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/// \return If target supports ds_read/write_b96/128.
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bool hasDS96AndDS128() const {
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return CIInsts;
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}
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/// Have v_trunc_f64, v_ceil_f64, v_rndne_f64
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bool haveRoundOpsF64() const {
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return CIInsts;
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@ -7951,9 +7951,12 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("unsupported private_element_size");
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}
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} else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
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// Use ds_read_b128 if possible.
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if (Subtarget->useDS128() && Load->getAlignment() >= 16 &&
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MemVT.getStoreSize() == 16)
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// Use ds_read_b128 or ds_read_b96 when possible.
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if (Subtarget->hasDS96AndDS128() &&
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((Subtarget->useDS128() && MemVT.getStoreSize() == 16) ||
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MemVT.getStoreSize() == 12) &&
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allowsMisalignedMemoryAccessesImpl(MemVT.getSizeInBits(), AS,
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Load->getAlign()))
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return SDValue();
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if (NumElements > 2)
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@ -8421,9 +8424,12 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("unsupported private_element_size");
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}
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} else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
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// Use ds_write_b128 if possible.
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if (Subtarget->useDS128() && Store->getAlignment() >= 16 &&
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VT.getStoreSize() == 16 && NumElements != 3)
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// Use ds_write_b128 or ds_write_b96 when possible.
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if (Subtarget->hasDS96AndDS128() &&
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((Subtarget->useDS128() && VT.getStoreSize() == 16) ||
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(VT.getStoreSize() == 12)) &&
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allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AS,
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Store->getAlign()))
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return SDValue();
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if (NumElements > 2)
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@ -473,8 +473,9 @@ define amdgpu_kernel void @load_constant_disjoint_offsets(i32 addrspace(1)* %out
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], bar@abs32@lo{{$}}
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; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:2 offset1:3
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; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset1:1
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; CI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset1:1
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; CI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:2 offset1:3
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; GFX9: ds_read_b128 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]]
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define amdgpu_kernel void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
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%val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
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%val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
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@ -438,8 +438,10 @@ define amdgpu_kernel void @store_constant_disjoint_offsets() {
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], bar@abs32@lo{{$}}
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; GCN-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
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; GCN-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; CI-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
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; CI-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; GFX9-DAG: ds_write_b128 [[PTR]], {{v\[[0-9]+:[0-9]+\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @store_misaligned64_constant_offsets() {
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store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
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@ -509,8 +511,9 @@ define amdgpu_kernel void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %ld
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; CI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:2 offset1:3{{$}}
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; GCN-DAG: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
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; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
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; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:2 offset1:3{{$}}
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; GFX9: ds_write_b128 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 {
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%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%in.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in
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@ -4,10 +4,8 @@
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; an unused stack slot, causing ScratchSize to be non-zero.
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; GCN-LABEL: store_v3i32:
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; GCN: ds_read_b32
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; GCN: ds_read_b64
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; GCN: ds_write_b32
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; GCN: ds_write_b64
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; GCN: ds_read_b96
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; GCN: ds_write_b96
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; GCN: ScratchSize: 0
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define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> %a) nounwind {
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%val = load <3 x i32>, <3 x i32> addrspace(3)* %out
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@ -21,10 +21,8 @@ bb:
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}
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; GCN-LABEL: test_local_misaligned_v4:
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; GCN-DAG: ds_read2_b32
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; GCN-DAG: ds_read2_b32
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; GCN-DAG: ds_write2_b32
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; GCN-DAG: ds_write2_b32
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; GCN-DAG: ds_read_b128
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; GCN-DAG: ds_write_b128
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define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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@ -44,10 +42,8 @@ bb:
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}
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; GCN-LABEL: test_local_misaligned_v3:
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; GCN-DAG: ds_read2_b32
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; GCN-DAG: ds_read_b32
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; GCN-DAG: ds_write2_b32
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_read_b96
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; GCN-DAG: ds_write_b96
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define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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@ -159,10 +155,8 @@ bb:
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}
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; GCN-LABEL: test_local_aligned_v3:
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; GCN-DAG: ds_read_b64
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; GCN-DAG: ds_read_b32
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; GCN-DAG: ds_write_b64
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_read_b96
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; GCN-DAG: ds_write_b96
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define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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@ -218,8 +212,8 @@ bb:
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}
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; GCN-LABEL: test_local_v4_aligned8:
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; GCN-DAG: ds_read2_b64
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; GCN-DAG: ds_write2_b64
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; GCN-DAG: ds_read_b128
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; GCN-DAG: ds_write_b128
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define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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@ -40,11 +40,13 @@ entry:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8
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; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}}
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8
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; SI-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}}
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; CIVI-DAG: ds_read_b96 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}}
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; GCN: s_waitcnt
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; GCN-DAG: ds_write_b64
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; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8{{$}}
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; SI-DAG: ds_write_b64
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; SI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8{{$}}
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; CIVI-DAG: ds_write_b96 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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@ -232,8 +232,10 @@ define amdgpu_kernel void @local_sextload_v2i16_to_v2i32(<2 x i32> addrspace(3)*
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; SICIVI: s_mov_b32 m0
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; GCN: ds_read_b64
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_write_b64
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_write_b64
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; CIVI-DAG: ds_write_b96
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; GFX9-DAG: ds_write_b96
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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@ -251,8 +253,10 @@ entry:
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; SICIVI: s_mov_b32 m0
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; GCN: ds_read_b64
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_write_b64
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; SI-DAG: ds_write_b32
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; SI-DAG: ds_write_b64
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; CIVI-DAG: ds_write_b96
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; GFX9-DAG: ds_write_b96
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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@ -39,8 +39,9 @@ entry:
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; SICIVI: s_mov_b32 m0, -1
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; GFX9-NOT: m0
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; GCN-DAG: ds_read_b64
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; GCN-DAG: ds_read_b32
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; SI-DAG: ds_read_b64
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; SI-DAG: ds_read_b32
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; CIVI-DAG: ds_read_b96
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define amdgpu_kernel void @local_load_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> addrspace(3)* %in) #0 {
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entry:
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%ld = load <3 x i32>, <3 x i32> addrspace(3)* %in
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@ -207,8 +207,10 @@ entry:
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; GCN-DAG: v_bfe_i32
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; GCN-DAG: v_bfe_i32
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; GCN-DAG: ds_write_b64
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; GCN-DAG: ds_write_b32
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; SI-DAG: ds_write_b64
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; SI-DAG: ds_write_b32
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; CIVI-DAG: ds_write_b96
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; GFX9-DAG: ds_write_b96
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; EG: LDS_READ_RET
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; EG-DAG: BFE_INT
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@ -0,0 +1,378 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
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define <4 x i32> @load_lds_v4i32(<4 x i32> addrspace(3)* %ptr) {
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; GFX9-LABEL: load_lds_v4i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: ds_read_b128 v[0:3], v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: load_lds_v4i32:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: ds_read_b128 v[0:3], v0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX6-LABEL: load_lds_v4i32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
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; GFX6-NEXT: s_mov_b32 m0, -1
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; GFX6-NEXT: ds_read_b64 v[2:3], v1
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; GFX6-NEXT: ds_read_b64 v[0:1], v0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr
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ret <4 x i32> %load
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}
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define <4 x i32> @load_lds_v4i32_align1(<4 x i32> addrspace(3)* %ptr) {
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; GFX9-LABEL: load_lds_v4i32_align1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: ds_read_u8 v1, v0
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; GFX9-NEXT: ds_read_u8 v2, v0 offset:1
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; GFX9-NEXT: ds_read_u8 v3, v0 offset:2
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; GFX9-NEXT: ds_read_u8 v4, v0 offset:3
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; GFX9-NEXT: ds_read_u8 v5, v0 offset:4
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; GFX9-NEXT: ds_read_u8 v6, v0 offset:5
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; GFX9-NEXT: ds_read_u8 v7, v0 offset:6
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; GFX9-NEXT: ds_read_u8 v8, v0 offset:7
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; GFX9-NEXT: ds_read_u8 v9, v0 offset:8
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; GFX9-NEXT: ds_read_u8 v10, v0 offset:9
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; GFX9-NEXT: ds_read_u8 v11, v0 offset:10
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; GFX9-NEXT: ds_read_u8 v12, v0 offset:11
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; GFX9-NEXT: ds_read_u8 v13, v0 offset:12
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; GFX9-NEXT: ds_read_u8 v14, v0 offset:13
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; GFX9-NEXT: ds_read_u8 v15, v0 offset:14
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; GFX9-NEXT: ds_read_u8 v16, v0 offset:15
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; GFX9-NEXT: s_waitcnt lgkmcnt(14)
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; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(12)
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; GFX9-NEXT: v_lshl_or_b32 v1, v4, 8, v3
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; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(10)
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; GFX9-NEXT: v_lshl_or_b32 v1, v6, 8, v5
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; GFX9-NEXT: s_waitcnt lgkmcnt(8)
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; GFX9-NEXT: v_lshl_or_b32 v2, v8, 8, v7
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; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(6)
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; GFX9-NEXT: v_lshl_or_b32 v2, v10, 8, v9
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; GFX9-NEXT: s_waitcnt lgkmcnt(4)
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; GFX9-NEXT: v_lshl_or_b32 v3, v12, 8, v11
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; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
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; GFX9-NEXT: s_waitcnt lgkmcnt(2)
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; GFX9-NEXT: v_lshl_or_b32 v3, v14, 8, v13
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_lshl_or_b32 v4, v16, 8, v15
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; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7-LABEL: load_lds_v4i32_align1:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: ds_read_u8 v1, v0 offset:7
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; GFX7-NEXT: ds_read_u8 v2, v0 offset:6
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; GFX7-NEXT: ds_read_u8 v3, v0 offset:5
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; GFX7-NEXT: ds_read_u8 v5, v0 offset:4
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; GFX7-NEXT: ds_read_u8 v4, v0 offset:3
|
||||
; GFX7-NEXT: ds_read_u8 v6, v0 offset:2
|
||||
; GFX7-NEXT: ds_read_u8 v7, v0 offset:1
|
||||
; GFX7-NEXT: ds_read_u8 v8, v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(7)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX7-NEXT: v_or_b32_e32 v4, v4, v6
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v5
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX7-NEXT: v_or_b32_e32 v4, v4, v7
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v3
|
||||
; GFX7-NEXT: ds_read_u8 v3, v0 offset:15
|
||||
; GFX7-NEXT: ds_read_u8 v5, v0 offset:14
|
||||
; GFX7-NEXT: ds_read_u8 v6, v0 offset:13
|
||||
; GFX7-NEXT: ds_read_u8 v7, v0 offset:12
|
||||
; GFX7-NEXT: ds_read_u8 v2, v0 offset:11
|
||||
; GFX7-NEXT: ds_read_u8 v8, v0 offset:10
|
||||
; GFX7-NEXT: ds_read_u8 v9, v0 offset:9
|
||||
; GFX7-NEXT: ds_read_u8 v0, v0 offset:8
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(7)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v8
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v9, 8, v9
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_or_b32_e32 v0, v9, v0
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v5
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v0
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v6
|
||||
; GFX7-NEXT: v_or_b32_e32 v0, v0, v7
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v4i32_align1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 5, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 7, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 6, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 9, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 11, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_u8 v2, v2
|
||||
; GFX6-NEXT: ds_read_u8 v3, v3
|
||||
; GFX6-NEXT: ds_read_u8 v4, v4
|
||||
; GFX6-NEXT: ds_read_u8 v5, v5
|
||||
; GFX6-NEXT: ds_read_u8 v6, v6
|
||||
; GFX6-NEXT: ds_read_u8 v7, v7
|
||||
; GFX6-NEXT: ds_read_u8 v1, v1
|
||||
; GFX6-NEXT: ds_read_u8 v8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v9, vcc, 14, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v10, vcc, 3, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v11, vcc, 2, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v7
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 10, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 13, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 12, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 15, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v0
|
||||
; GFX6-NEXT: ds_read_u8 v4, v4
|
||||
; GFX6-NEXT: ds_read_u8 v5, v5
|
||||
; GFX6-NEXT: ds_read_u8 v6, v6
|
||||
; GFX6-NEXT: ds_read_u8 v7, v7
|
||||
; GFX6-NEXT: ds_read_u8 v9, v9
|
||||
; GFX6-NEXT: ds_read_u8 v10, v10
|
||||
; GFX6-NEXT: ds_read_u8 v11, v11
|
||||
; GFX6-NEXT: ds_read_u8 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(7)
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(4)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 8, v7
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX6-NEXT: v_or_b32_e32 v4, v4, v9
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v3, v6
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 8, v10
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_or_b32_e32 v4, v4, v11
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v0, v8
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 1
|
||||
ret <4 x i32> %load
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lds_v4i32_align2(<4 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v4i32_align2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_u16 v1, v0
|
||||
; GFX9-NEXT: ds_read_u16 v2, v0 offset:2
|
||||
; GFX9-NEXT: ds_read_u16 v3, v0 offset:4
|
||||
; GFX9-NEXT: ds_read_u16 v4, v0 offset:6
|
||||
; GFX9-NEXT: ds_read_u16 v5, v0 offset:8
|
||||
; GFX9-NEXT: ds_read_u16 v6, v0 offset:10
|
||||
; GFX9-NEXT: ds_read_u16 v7, v0 offset:12
|
||||
; GFX9-NEXT: ds_read_u16 v8, v0 offset:14
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(6)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v1
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(4)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v3
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v2, v6, 16, v5
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v3, v8, 16, v7
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v4i32_align2:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_u16 v3, v0 offset:14
|
||||
; GFX7-NEXT: ds_read_u16 v4, v0 offset:12
|
||||
; GFX7-NEXT: ds_read_u16 v2, v0 offset:10
|
||||
; GFX7-NEXT: ds_read_u16 v5, v0 offset:8
|
||||
; GFX7-NEXT: ds_read_u16 v1, v0 offset:6
|
||||
; GFX7-NEXT: ds_read_u16 v6, v0 offset:4
|
||||
; GFX7-NEXT: ds_read_u16 v7, v0 offset:2
|
||||
; GFX7-NEXT: ds_read_u16 v0, v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(5)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_or_b32_e32 v0, v7, v0
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v6
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v5
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v4
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v4i32_align2:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 6, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 10, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 14, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 12, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 2, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_u16 v2, v2
|
||||
; GFX6-NEXT: ds_read_u16 v3, v3
|
||||
; GFX6-NEXT: ds_read_u16 v4, v4
|
||||
; GFX6-NEXT: ds_read_u16 v5, v5
|
||||
; GFX6-NEXT: ds_read_u16 v6, v6
|
||||
; GFX6-NEXT: ds_read_u16 v7, v7
|
||||
; GFX6-NEXT: ds_read_u16 v1, v1
|
||||
; GFX6-NEXT: ds_read_u16 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v3, v6
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 2
|
||||
ret <4 x i32> %load
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lds_v4i32_align4(<4 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v4i32_align4:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b128 v[0:3], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v4i32_align4:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
|
||||
; GFX7-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v4i32_align4:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 12, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b32 v2, v2
|
||||
; GFX6-NEXT: ds_read_b32 v3, v3
|
||||
; GFX6-NEXT: ds_read_b32 v1, v1
|
||||
; GFX6-NEXT: ds_read_b32 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4
|
||||
ret <4 x i32> %load
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lds_v4i32_align8(<4 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v4i32_align8:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b128 v[0:3], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v4i32_align8:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read2_b64 v[0:3], v0 offset1:1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v4i32_align8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b64 v[2:3], v1
|
||||
; GFX6-NEXT: ds_read_b64 v[0:1], v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8
|
||||
ret <4 x i32> %load
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lds_v4i32_align16(<4 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v4i32_align16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b128 v[0:3], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v4i32_align16:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_b128 v[0:3], v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v4i32_align16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b64 v[2:3], v1
|
||||
; GFX6-NEXT: ds_read_b64 v[0:1], v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 16
|
||||
ret <4 x i32> %load
|
||||
}
|
||||
|
|
@ -0,0 +1,331 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
|
||||
|
||||
define <3 x i32> @load_lds_v3i32(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b32 v2, v1
|
||||
; GFX6-NEXT: ds_read_b64 v[0:1], v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
||||
define <3 x i32> @load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32_align1:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_u8 v1, v0
|
||||
; GFX9-NEXT: ds_read_u8 v2, v0 offset:1
|
||||
; GFX9-NEXT: ds_read_u8 v3, v0 offset:2
|
||||
; GFX9-NEXT: ds_read_u8 v4, v0 offset:3
|
||||
; GFX9-NEXT: ds_read_u8 v5, v0 offset:4
|
||||
; GFX9-NEXT: ds_read_u8 v6, v0 offset:5
|
||||
; GFX9-NEXT: ds_read_u8 v7, v0 offset:6
|
||||
; GFX9-NEXT: ds_read_u8 v8, v0 offset:7
|
||||
; GFX9-NEXT: ds_read_u8 v9, v0 offset:8
|
||||
; GFX9-NEXT: ds_read_u8 v10, v0 offset:9
|
||||
; GFX9-NEXT: ds_read_u8 v11, v0 offset:10
|
||||
; GFX9-NEXT: ds_read_u8 v12, v0 offset:11
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(10)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v1
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(8)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 8, v3
|
||||
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(6)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v6, 8, v5
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(4)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v2, v8, 8, v7
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v2, v10, 8, v9
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v3, v12, 8, v11
|
||||
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32_align1:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_u8 v1, v0 offset:7
|
||||
; GFX7-NEXT: ds_read_u8 v2, v0 offset:6
|
||||
; GFX7-NEXT: ds_read_u8 v4, v0 offset:5
|
||||
; GFX7-NEXT: ds_read_u8 v5, v0 offset:4
|
||||
; GFX7-NEXT: ds_read_u8 v3, v0 offset:3
|
||||
; GFX7-NEXT: ds_read_u8 v6, v0 offset:2
|
||||
; GFX7-NEXT: ds_read_u8 v7, v0 offset:1
|
||||
; GFX7-NEXT: ds_read_u8 v8, v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(7)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(5)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(4)
|
||||
; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
|
||||
; GFX7-NEXT: ds_read_u8 v2, v0 offset:11
|
||||
; GFX7-NEXT: ds_read_u8 v4, v0 offset:10
|
||||
; GFX7-NEXT: ds_read_u8 v5, v0 offset:9
|
||||
; GFX7-NEXT: ds_read_u8 v0, v0 offset:8
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(7)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(5)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v6
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
|
||||
; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32_align1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 5, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 7, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 6, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 9, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 11, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_u8 v2, v2
|
||||
; GFX6-NEXT: ds_read_u8 v3, v3
|
||||
; GFX6-NEXT: ds_read_u8 v4, v4
|
||||
; GFX6-NEXT: ds_read_u8 v5, v5
|
||||
; GFX6-NEXT: ds_read_u8 v6, v6
|
||||
; GFX6-NEXT: ds_read_u8 v7, v7
|
||||
; GFX6-NEXT: ds_read_u8 v1, v1
|
||||
; GFX6-NEXT: ds_read_u8 v8, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 10, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 3, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 2, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v0
|
||||
; GFX6-NEXT: ds_read_u8 v4, v4
|
||||
; GFX6-NEXT: ds_read_u8 v5, v5
|
||||
; GFX6-NEXT: ds_read_u8 v6, v6
|
||||
; GFX6-NEXT: ds_read_u8 v0, v0
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v7
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v5
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_or_b32_e32 v3, v3, v6
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v0, v8
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
||||
define <3 x i32> @load_lds_v3i32_align2(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32_align2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_u16 v1, v0
|
||||
; GFX9-NEXT: ds_read_u16 v2, v0 offset:2
|
||||
; GFX9-NEXT: ds_read_u16 v3, v0 offset:4
|
||||
; GFX9-NEXT: ds_read_u16 v4, v0 offset:6
|
||||
; GFX9-NEXT: ds_read_u16 v5, v0 offset:8
|
||||
; GFX9-NEXT: ds_read_u16 v6, v0 offset:10
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(4)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v1
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v3
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_lshl_or_b32 v2, v6, 16, v5
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32_align2:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_u16 v2, v0 offset:10
|
||||
; GFX7-NEXT: ds_read_u16 v3, v0 offset:8
|
||||
; GFX7-NEXT: ds_read_u16 v1, v0 offset:6
|
||||
; GFX7-NEXT: ds_read_u16 v4, v0 offset:4
|
||||
; GFX7-NEXT: ds_read_u16 v5, v0 offset:2
|
||||
; GFX7-NEXT: ds_read_u16 v0, v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(5)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(3)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(2)
|
||||
; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
|
||||
; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32_align2:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 6, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 10, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 8, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_u16 v2, v2
|
||||
; GFX6-NEXT: ds_read_u16 v3, v3
|
||||
; GFX6-NEXT: ds_read_u16 v4, v4
|
||||
; GFX6-NEXT: ds_read_u16 v5, v5
|
||||
; GFX6-NEXT: ds_read_u16 v1, v1
|
||||
; GFX6-NEXT: ds_read_u16 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(1)
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
|
||||
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
|
||||
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 2
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
||||
define <3 x i32> @load_lds_v3i32_align4(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32_align4:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32_align4:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
|
||||
; GFX7-NEXT: ds_read_b32 v2, v2 offset:8
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32_align4:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b32 v2, v2
|
||||
; GFX6-NEXT: ds_read_b32 v1, v1
|
||||
; GFX6-NEXT: ds_read_b32 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
||||
define <3 x i32> @load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32_align8:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32_align8:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
|
||||
; GFX7-NEXT: ds_read_b32 v2, v2 offset:8
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32_align8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
||||
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b32 v2, v2
|
||||
; GFX6-NEXT: ds_read_b32 v1, v1
|
||||
; GFX6-NEXT: ds_read_b32 v0, v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
||||
define <3 x i32> @load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) {
|
||||
; GFX9-LABEL: load_lds_v3i32_align16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX7-LABEL: load_lds_v3i32_align16:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: ds_read_b96 v[0:2], v0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX6-LABEL: load_lds_v3i32_align16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: ds_read_b32 v2, v1
|
||||
; GFX6-NEXT: ds_read_b64 v[0:1], v0
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: s_setpc_b64 s[30:31]
|
||||
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
|
||||
ret <3 x i32> %load
|
||||
}
|
||||
|
|
@ -0,0 +1,422 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX7-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX6-NEXT: ds_write2_b64 v4, v[2:3], v[0:1] offset1:1
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32_align1:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: s_lshr_b32 s4, s2, 8
|
||||
; GFX9-NEXT: s_lshr_b32 s2, s2, 24
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s2
|
||||
; GFX9-NEXT: s_lshr_b32 s2, s3, 8
|
||||
; GFX9-NEXT: v_mov_b32_e32 v6, s0
|
||||
; GFX9-NEXT: ds_write_b8 v0, v2 offset:8
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:10
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: s_lshr_b32 s2, s0, 8
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX9-NEXT: v_mov_b32_e32 v8, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s1, 8
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, s1
|
||||
; GFX9-NEXT: ds_write_b8 v0, v6
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v6 offset:2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v6, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s3, 24
|
||||
; GFX9-NEXT: ds_write_b8 v0, v1 offset:12
|
||||
; GFX9-NEXT: ds_write_b8 v0, v5 offset:4
|
||||
; GFX9-NEXT: ds_write_b8 v0, v2 offset:13
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s1, 24
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:14
|
||||
; GFX9-NEXT: ds_write_b8 v0, v2 offset:15
|
||||
; GFX9-NEXT: ds_write_b8 v0, v3 offset:9
|
||||
; GFX9-NEXT: ds_write_b8 v0, v4 offset:11
|
||||
; GFX9-NEXT: ds_write_b8 v0, v6 offset:5
|
||||
; GFX9-NEXT: v_mov_b32_e32 v7, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v5 offset:6
|
||||
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX9-NEXT: ds_write_b8 v0, v7 offset:1
|
||||
; GFX9-NEXT: ds_write_b8 v0, v8 offset:3
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32_align1:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: s_lshr_b32 s4, s3, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v5, s4
|
||||
; GFX7-NEXT: s_lshr_b32 s4, s3, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX7-NEXT: s_lshr_b32 s3, s3, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v5 offset:13
|
||||
; GFX7-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX7-NEXT: s_lshr_b32 s3, s2, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v6, s4
|
||||
; GFX7-NEXT: ds_write_b8 v0, v5 offset:15
|
||||
; GFX7-NEXT: ds_write_b8 v0, v6 offset:14
|
||||
; GFX7-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s3, s2, 16
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s2, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v2 offset:8
|
||||
; GFX7-NEXT: ds_write_b8 v0, v5 offset:9
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s1, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v6, s3
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:12
|
||||
; GFX7-NEXT: ds_write_b8 v0, v2 offset:11
|
||||
; GFX7-NEXT: ds_write_b8 v0, v6 offset:10
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s1, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s1, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s0, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX7-NEXT: ds_write_b8 v0, v2 offset:6
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s0, 16
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v4
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX7-NEXT: ds_write_b8 v0, v3 offset:4
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:3
|
||||
; GFX7-NEXT: ds_write_b8 v0, v2 offset:2
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32_align1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: s_lshr_b32 s4, s3, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v5, s4
|
||||
; GFX6-NEXT: s_lshr_b32 s4, s3, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: s_lshr_b32 s3, s3, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v5 offset:13
|
||||
; GFX6-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX6-NEXT: s_lshr_b32 s3, s2, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v6, s4
|
||||
; GFX6-NEXT: ds_write_b8 v0, v5 offset:15
|
||||
; GFX6-NEXT: ds_write_b8 v0, v6 offset:14
|
||||
; GFX6-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s3, s2, 16
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v2 offset:8
|
||||
; GFX6-NEXT: ds_write_b8 v0, v5 offset:9
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s1, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v6, s3
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:12
|
||||
; GFX6-NEXT: ds_write_b8 v0, v2 offset:11
|
||||
; GFX6-NEXT: ds_write_b8 v0, v6 offset:10
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s1, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s1, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s0, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX6-NEXT: ds_write_b8 v0, v2 offset:6
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v4
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX6-NEXT: ds_write_b8 v0, v3 offset:4
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:3
|
||||
; GFX6-NEXT: ds_write_b8 v0, v2 offset:2
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32_align2(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32_align2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:14
|
||||
; GFX9-NEXT: ds_write_b16 v0, v4
|
||||
; GFX9-NEXT: ds_write_b16 v0, v3 offset:4
|
||||
; GFX9-NEXT: ds_write_b16 v0, v2 offset:8
|
||||
; GFX9-NEXT: ds_write_b16 v0, v1 offset:12
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:10
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v3 offset:6
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v4 offset:2
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32_align2:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s0, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v5, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX7-NEXT: ds_write_b16 v0, v4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: ds_write_b16 v0, v3 offset:4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s3, 16
|
||||
; GFX7-NEXT: ds_write_b16 v0, v2 offset:8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX7-NEXT: ds_write_b16 v0, v2 offset:14
|
||||
; GFX7-NEXT: ds_write_b16 v0, v1 offset:12
|
||||
; GFX7-NEXT: ds_write_b16 v0, v3 offset:10
|
||||
; GFX7-NEXT: ds_write_b16 v0, v4 offset:6
|
||||
; GFX7-NEXT: ds_write_b16 v0, v5 offset:2
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32_align2:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v5, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX6-NEXT: ds_write_b16 v0, v4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX6-NEXT: ds_write_b16 v0, v3 offset:4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s3, 16
|
||||
; GFX6-NEXT: ds_write_b16 v0, v2 offset:8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: ds_write_b16 v0, v2 offset:14
|
||||
; GFX6-NEXT: ds_write_b16 v0, v1 offset:12
|
||||
; GFX6-NEXT: ds_write_b16 v0, v3 offset:10
|
||||
; GFX6-NEXT: ds_write_b16 v0, v4 offset:6
|
||||
; GFX6-NEXT: ds_write_b16 v0, v5 offset:2
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32_align4:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32_align4:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s3
|
||||
; GFX7-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
|
||||
; GFX7-NEXT: ds_write2_b32 v0, v3, v4 offset0:2 offset1:3
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32_align4:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: ds_write2_b32 v0, v2, v1 offset1:1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX6-NEXT: ds_write2_b32 v0, v2, v1 offset0:2 offset1:3
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32_align8(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32_align8:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32_align8:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX7-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32_align8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX6-NEXT: ds_write2_b64 v4, v[2:3], v[0:1] offset1:1
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v4i32_align16(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v4i32_align16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v4i32_align16:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX7-NEXT: ds_write_b128 v4, v[0:3]
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v4i32_align16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX6-NEXT: ds_write2_b64 v4, v[2:3], v[0:1] offset1:1
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,370 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: ds_write_b32 v2, v3 offset:8
|
||||
; GFX6-NEXT: ds_write_b64 v2, v[0:1]
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32_align1:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-NEXT: s_lshr_b32 s3, s2, 8
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s3
|
||||
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX9-NEXT: v_mov_b32_e32 v6, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s1, 8
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
||||
; GFX9-NEXT: ds_write_b8 v0, v4
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v4 offset:2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s2, 24
|
||||
; GFX9-NEXT: ds_write_b8 v0, v1 offset:8
|
||||
; GFX9-NEXT: ds_write_b8 v0, v3 offset:4
|
||||
; GFX9-NEXT: ds_write_b8 v0, v2 offset:9
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX9-NEXT: s_lshr_b32 s0, s1, 24
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:10
|
||||
; GFX9-NEXT: ds_write_b8 v0, v2 offset:11
|
||||
; GFX9-NEXT: ds_write_b8 v0, v4 offset:5
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX9-NEXT: ds_write_b8_d16_hi v0, v3 offset:6
|
||||
; GFX9-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX9-NEXT: ds_write_b8 v0, v5 offset:1
|
||||
; GFX9-NEXT: ds_write_b8 v0, v6 offset:3
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32_align1:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: s_lshr_b32 s3, s2, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s3
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s3, s2, 16
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s2, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:8
|
||||
; GFX7-NEXT: ds_write_b8 v0, v4 offset:9
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s1, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:11
|
||||
; GFX7-NEXT: ds_write_b8 v0, v5 offset:10
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s1, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s1, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:5
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s0, 8
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s2
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX7-NEXT: ds_write_b8 v0, v4 offset:6
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s1, s0, 16
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX7-NEXT: ds_write_b8 v0, v3
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX7-NEXT: ds_write_b8 v0, v2 offset:4
|
||||
; GFX7-NEXT: ds_write_b8 v0, v1 offset:3
|
||||
; GFX7-NEXT: ds_write_b8 v0, v4 offset:2
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32_align1:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: s_lshr_b32 s3, s2, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s3, s2, 16
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:8
|
||||
; GFX6-NEXT: ds_write_b8 v0, v4 offset:9
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s1, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v5, s3
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:11
|
||||
; GFX6-NEXT: ds_write_b8 v0, v5 offset:10
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: s_lshr_b32 s2, s1, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s1, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:5
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s0, 8
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s2
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:7
|
||||
; GFX6-NEXT: ds_write_b8 v0, v4 offset:6
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
|
||||
; GFX6-NEXT: ds_write_b8 v0, v3
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX6-NEXT: ds_write_b8 v0, v2 offset:4
|
||||
; GFX6-NEXT: ds_write_b8 v0, v1 offset:3
|
||||
; GFX6-NEXT: ds_write_b8 v0, v4 offset:2
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32_align2(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32_align2:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1 offset:10
|
||||
; GFX9-NEXT: ds_write_b16 v0, v3
|
||||
; GFX9-NEXT: ds_write_b16 v0, v2 offset:4
|
||||
; GFX9-NEXT: ds_write_b16 v0, v1 offset:8
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v2 offset:6
|
||||
; GFX9-NEXT: ds_write_b16_d16_hi v0, v3 offset:2
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32_align2:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s0, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s1, 16
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX7-NEXT: ds_write_b16 v0, v3
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX7-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX7-NEXT: ds_write_b16 v0, v2 offset:4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX7-NEXT: ds_write_b16 v0, v2 offset:10
|
||||
; GFX7-NEXT: ds_write_b16 v0, v1 offset:8
|
||||
; GFX7-NEXT: ds_write_b16 v0, v3 offset:6
|
||||
; GFX7-NEXT: ds_write_b16 v0, v4 offset:2
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32_align2:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v4, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s1, 16
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX6-NEXT: ds_write_b16 v0, v3
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s0
|
||||
; GFX6-NEXT: s_lshr_b32 s0, s2, 16
|
||||
; GFX6-NEXT: ds_write_b16 v0, v2 offset:4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: ds_write_b16 v0, v2 offset:10
|
||||
; GFX6-NEXT: ds_write_b16 v0, v1 offset:8
|
||||
; GFX6-NEXT: ds_write_b16 v0, v3 offset:6
|
||||
; GFX6-NEXT: ds_write_b16 v0, v4 offset:2
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32_align4(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32_align4:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32_align4:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX7-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
|
||||
; GFX7-NEXT: ds_write_b32 v0, v3 offset:8
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32_align4:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX6-NEXT: ds_write2_b32 v0, v2, v1 offset1:1
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s2
|
||||
; GFX6-NEXT: ds_write_b32 v0, v1 offset:8
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32_align8(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32_align8:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32_align8:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: ds_write_b32 v2, v3 offset:8
|
||||
; GFX7-NEXT: ds_write_b64 v2, v[0:1]
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32_align8:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: ds_write_b32 v2, v3 offset:8
|
||||
; GFX6-NEXT: ds_write_b64 v2, v[0:1]
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @store_lds_v3i32_align16(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
|
||||
; GFX9-LABEL: store_lds_v3i32_align16:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x24
|
||||
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX7-LABEL: store_lds_v3i32_align16:
|
||||
; GFX7: ; %bb.0:
|
||||
; GFX7-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 m0, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: v_mov_b32_e32 v3, s4
|
||||
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX7-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX7-NEXT: ds_write_b96 v3, v[0:2]
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX6-LABEL: store_lds_v3i32_align16:
|
||||
; GFX6: ; %bb.0:
|
||||
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
|
||||
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
|
||||
; GFX6-NEXT: s_mov_b32 m0, -1
|
||||
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX6-NEXT: v_mov_b32_e32 v2, s4
|
||||
; GFX6-NEXT: v_mov_b32_e32 v3, s2
|
||||
; GFX6-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX6-NEXT: ds_write_b32 v2, v3 offset:8
|
||||
; GFX6-NEXT: ds_write_b64 v2, v[0:1]
|
||||
; GFX6-NEXT: s_endpgm
|
||||
store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
|
@ -179,8 +179,9 @@ entry:
|
|||
; CM: LDS_WRITE
|
||||
; CM: LDS_WRITE
|
||||
|
||||
; GCN: ds_write2_b32
|
||||
; GCN: ds_write2_b32
|
||||
; SICIVI: ds_write2_b32
|
||||
; SICIVI: ds_write2_b32
|
||||
; GFX9: ds_write_b128
|
||||
define amdgpu_kernel void @store_local_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
|
||||
entry:
|
||||
store <4 x i32> %in, <4 x i32> addrspace(3)* %out, align 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue